參數(shù)資料
型號: 24LCS41A
廠商: Microchip Technology Inc.
英文描述: 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,2.5V雙模式,雙端口IIC串行EEPROM)
中文描述: 1K/4K 2.5V的雙模式,雙端口串行EEPROM國際進口證(1K/4K位,2.5V的雙模式,雙端口串行EEPROM的國際進口許可證)
文件頁數(shù): 9/16頁
文件大?。?/td> 104K
代理商: 24LCS41A
1996 Microchip Technology Inc.
Preliminary
DS21175A-page 9
24LCS41A
4.0
WRITE OPERATION
Write operations are identical for the DDC Monitor Port
(when in Bi-directional Mode) and the Microcontroller
Access Port, with the exception of the VCLK and DWP
pins noted in the next sections. Data can be written
using either a byte write or page write command. Write
commands for the DDC Monitor Port and the Microcon-
troller Access Port are completely independent of one
another.
4.1
Byte Write
Following the start signal from the master, the slave
address (4-bits), the chip select bits (3-bits) and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the port. After receiving
another acknowledge signal from the port, the master
device will transmit the data word to be written into the
addressed memory location. The port acknowledges
again and the master generates a stop condition. This
initiates the internal write cycle, and during this time,
the port will not generate acknowledge signals
(Figure 4-1).
For the DDC Monitor Port it is required that VCLK be
held at a logic high level in order to program the device.
This applies to byte write and page write operation.
Note that VCLK can go low while the device is in its self-
timed program operation and not affect programming.
The DWP pin must be held high for the duration of the
write protection.
4.2
Page Write
The write control byte, word address, and the first data
byte are transmitted to the port in the same way as in a
byte write. But, instead of generating a stop condition,
the master transmits up to eight data bytes to the DDC
Monitor Port or 16 bytes to the Microcontroller Access
Port, which are temporarily stored in the on-chip page
buffer and will be written into the memory after the mas-
ter has transmitted a stop condition. After the receipt of
each word, the three lower order address pointer bits
are internally incremented by one. The higher order 5-
bits of the word address remains constant. If the master
should transmit more than eight words to the DDC Mon-
itor Port or 16 words to the Microcontroller Access Port
prior to generating the stop condition, the address
counter will roll over and the previously received data
will be overwritten. As with the byte write operation,
once the stop condition is received an internal write
cycle will begin (Figure 4-2).
For the DDC Monitor Port, it is required thatVCLK be
held at a logic high level in order to program the device.
This applies to byte write and page write operation.
Note that VCLK can go low while the device is in its self-
timed program operation and not affect programming.
For the DDC Monitor Port, the DWP pin must be held
high for the duration of the write cycle.
FIGURE 4-1:
BYTE WRITE
S
P
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
MASTER
SDA or
MSDA LINE
BUS ACTIVITY
A
C
K
A
C
K
A
C
K
CONTROL
BYTE
WORD
ADDRESS
DATA
VCLK
相關(guān)PDF資料
PDF描述
24LCS41 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,2.5V雙模式,雙端口IIC串行EEPROM)
24LCS52 Connectors
24LC52-IP 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-ISN 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-IST 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
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