參數(shù)資料
型號(hào): 24LCS41A
廠商: Microchip Technology Inc.
英文描述: 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,2.5V雙模式,雙端口IIC串行EEPROM)
中文描述: 1K/4K 2.5V的雙模式,雙端口串行EEPROM國(guó)際進(jìn)口證(1K/4K位,2.5V的雙模式,雙端口串行EEPROM的國(guó)際進(jìn)口許可證)
文件頁(yè)數(shù): 3/16頁(yè)
文件大小: 104K
代理商: 24LCS41A
1996 Microchip Technology Inc.
Preliminary
DS21175A-page 3
24LCS41A
TABLE 1-3:
AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS
PORTS)
DDC Monitor Port (Bi-directional Mode) and Microcontroller Access Port
Parameter
Symbol
Standard Mode
Vcc = 4.5 - 5.5V
Fast Mode
Units
Remarks
Min
Max
100
Min
Max
400
Clock frequency (DSCL and
MSCL)
Clock high time (DSCL and
MSCL)
Clock low time (DSCL and
MSCL)
DSCL, DSDA, MSCL &
MSDA rise time
DSCL, DSDA, MSCL &
MSDA fall time
START condition hold time
F
CLK
kHz
T
HIGH
4000
600
ns
T
LOW
4700
1300
ns
T
R
1000
300
ns
(Note 1)
T
F
300
300
ns
(Note 1)
T
HD
:
STA
4000
600
ns
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
(Note 2)
START condition setup time T
SU
:
STA
4700
600
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
T
T
T
HD
:
:
:
DAT
0
0
900
ns
ns
ns
ns
ns
SU
DAT
250
4000
4700
100
600
1300
SU
T
T
STO
AA
3500
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
BUF
Output fall time from V
min to V
IL
max
Input filter spike suppres-
sion (DSCL, DSDA, MSCL
& MSDA pins)
Write cycle time
Endurance
IH
T
OF
250
20 + .1
C
B
250
ns
100 pF
T
SP
50
50
ns
(Note 3)
T
WR
10M
10
10M
10
ms
cycles
Byte or Page mode
25
°
C, Vcc = 5.0V, Block Mode
(Note 4)
DDC Monitor Port Transmit-Only Mode Parameters
Output valid from VCLK
VCLK high time
VCLK low time
VCLK setup time
VCLK hold time
Mode transition time
Transmit-Only power up time
Input filter spike suppression
(VCLK pin)
Note 1: Not 100% tested. C
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of START or STOP
conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
T
VAA
2000
500
100
600
1300
0
600
0
1000
500
100
ns
ns
ns
ns
ns
ns
ns
ns
T
T
T
T
VHIGH
4000
4700
0
4000
0
VLOW
VHST
SPVL
T
VHZ
T
VPU
T
SPV
B
= total capacitance of one bus line in pF.
I
specification for standard operation.
相關(guān)PDF資料
PDF描述
24LCS41 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,2.5V雙模式,雙端口IIC串行EEPROM)
24LCS52 Connectors
24LC52-IP 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-ISN 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
24LC52-IST 2K 2.5V I 2 C Serial EEPROM with Software Write Protect
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