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參數(shù)資料
| 型號(hào)： | 24LCS21 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 1K 2.5V Dual Mode I 2 C Serial EEPROM |
| 中文描述： | 一千2.5V的雙模式的I 2 C串行EEPROM |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 91K |
| 代理商： | 24LCS21 |
1996 Microchip Technology Inc.
DS21127B-page 7
24LCS21
3.1.6
SLAVE ADDRESS
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LCS21.
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LCS21
(Figure 3-5).
The 24LCS21 monitors the bus for its corresponding
slave
address
continuously.
acknowledge bit if the slave address was true and it is
not in a programming mode.
It
generates
an
FIGURE 3-5: CONTROL BYTE ALLOCATION
Operation
Slave Address
R/W
Read
1010000
1
Write
1010000
0
SLAVE ADDRESS
1
0
1
0
0
0
0
R/W
A
START
READ/WRITE
4.0
WRITE OPERATION
4.1
Byte Write
Following the start signal from the master, the slave
address (4 bits), three zero bits (000) and the R/W bit
which is a logic low are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24LCS21. After receiving
another acknowledge signal from the 24LCS21 the
master device will transmit the data word to be written
into the addressed memory location. The 24LCS21
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24LCS21 will not generate acknowl-
edge signals (Figure 4-1).
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high to low during the self-timed
program operation will not halt programming of the
device.
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: VCLK WRITE ENABLE TIMING
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
CONTROL
BYTE
WORD
ADDRESS
DATA
S
T
O
P
S
T
A
R
T
A
C
K
S
P
A
C
K
A
C
K
VCLK
T
SPVL
T
SU
:
STO
T
HD
:
STA
T
VHST
VCLK
SDA
IN
SCL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24LCS41A | 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,2.5V雙模式,雙端口IIC串行EEPROM) |
| 24LCS41 | 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,2.5V雙模式,雙端口IIC串行EEPROM) |
| 24LCS52 | Connectors |
| 24LC52-IP | 2K 2.5V I 2 C Serial EEPROM with Software Write Protect |
| 24LC52-ISN | 2K 2.5V I 2 C Serial EEPROM with Software Write Protect |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LCS21A/P | 功能描述:電可擦除可編程只讀存儲(chǔ)器 2.5V Dual Mode RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LCS21A/S | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPRO - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LCS21A/SN | 功能描述:電可擦除可編程只讀存儲(chǔ)器 2.5V Dual Mode RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LCS21A/W | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPROM WAFER - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LCS21A/WF | 制造商:Microchip Technology Inc 功能描述:1K 2.5V DUAL MODE SERIAL EEPRO - Gel-pak, waffle pack, wafer, diced wafer on film |
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