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參數資料
| 型號： | 24LC41 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 1K/4K 2.5V Dual Mode, Dual Port I 2 C Serial EEPROM |
| 中文描述： | 1K/4K 2.5V的雙模式，雙端口的I 2 C串行EEPROM |
| 文件頁數： | 6/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | 24LC41 |
24LC41
DS21140B-page 6
1996 Microchip Technology Inc.
3.0
BI-DIRECTIONAL BUS
CHARACTERISTICS
Characteristics for the bi-directional bus are identical
for both the DDC Monitor Port (in bi-directional Mode)
and the Microcontroller Access Port The following
bus
protocol
has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is HIGH determines a
START condition. All commands must be preceded by
a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the DSDA or MSDA line
while the clock (DSCL or MSCL) is HIGH determines a
STOP condition. All operations must be ended with a
STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight will be stored when doing a write operation. When
an overwrite does occur, it will replace data in a first in
first out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit
.
Note:
The microcontroller access port and the
DDC Monitor Port (in bi-directional Mode)
will not generate any acknowledge bits if an
internal programming cycle is in progress.
The device that acknowledges has to pull down the
DSDA or MSDA line during the acknowledge clock
pulse in such a way that the DSDA or MSDA line is sta-
ble LOW during the HIGH period of the acknowledge
related clock pulse. Of course, setup and hold times
must be taken into account. A master must signal an
end of data to the slave by not generating an acknowl-
edge bit on the last byte that has been clocked out of
the slave. In this case, the slave must leave the data line
HIGH to enable the master to generate the STOP con-
dition.
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The first part of
the control byte consists of a 4-bit control code. This
control code is set as 1010 for both read and write oper-
ations and is the same for both the DDC Monitor Port
and Microcontroller Access Port. The next three bits of
the control byte are block select bits (B1, B2, and B0).
All three of these bits are don’t care bits for the DDC
Monitor Port. The B2 and B1 bits are don’t care bits for
the Microcontroller Access Port, and the B0 bit is used
by the Microcontroller Access Port to select which of
the two 256 word blocks of memory are to be accessed
(Figure 3-4). The B0 bit is effectively the most signifi-
cant bit of the word address. The last bit of the control
byte defines the operation to be performed. When set
to one, a read operation is selected; when set to zero,
a write operation is selected. Following the start condi-
tion, the device monitors the DSDA or MSDA bus
checking the device type identifier being transmitted,
upon a 1010 code the slave device outputs an acknowl-
edge signal on the SDA line. Depending on the state of
the R/W bit, the device will select a read or a write oper-
ation. The DDC Monitor Port and Microcontroller
Access Port can be accessed simultaneously because
they are completely independent of one another.
Operation
Control Code
Chip Select
R/W
Read
Write
1010
1010
XXB0
XXB0
1
0
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 24LC512/S16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512/W16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND,WAFER - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512/WF16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512-E/MF | 功能描述:電可擦除可編程只讀存儲器 64kx8 - 2.5V RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC512-E/MS | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE, EXT - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC EEPROM 512KBIT 400KHZ 8MSOP 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE, EXT, 8 MSOP 3x3mm TUBE |
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