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參數(shù)資料
| 型號(hào)： | 24LC41 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 1K/4K 2.5V Dual Mode, Dual Port I 2 C Serial EEPROM |
| 中文描述： | 1K/4K 2.5V的雙模式，雙端口的I 2 C串行EEPROM |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | 24LC41 |
1996 Microchip Technology Inc.
DS21140B-page 3
24LC41
TABLE 1-3:
AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS
PORTS)
DDC Monitor Port (Bi-directional Mode) and Microcontroller Access Port
Parameter
Symbol
Standard Mode
Vcc = 4.5 - 5.5V
Fast Mode
Units
Remarks
Min
—
Max
100
Min
—
Max
400
Clock frequency (DSCL and
MSCL)
Clock high time (DSCL and
MSCL)
Clock low time (DSCL and
MSCL)
DSCL, DSDA, MSCL &
MSDA rise time
DSCL, DSDA, MSCL &
MSDA fall time
START condition hold time
F
CLK
kHz
T
HIGH
4000
—
600
—
ns
T
LOW
4700
—
1300
—
ns
T
R
—
1000
—
300
ns
(Note 1)
T
F
—
300
—
300
ns
(Note 1)
T
HD
:
STA
4000
—
600
—
ns
After this period the first
clock pulse is generated
Only relevant for repeated
START condition
(Note 2)
START condition setup time T
SU
:
STA
4700
—
600
—
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
T
T
T
T
T
HD
:
:
:
DAT
0
—
—
—
0
—
—
—
900
—
ns
ns
ns
ns
ns
SU
DAT
250
4000
—
4700
100
600
—
1300
SU
STO
AA
3500
—
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
≤
BUF
Output fall time from V
min to V
IL
max
Input filter spike suppres-
sion (DSCL, DSDA, MSCL
& MSDA pins)
Write cycle time
DDC Monitor Port Transmit-Only Mode Parameters
Output valid from VCLK/
DWP
VCLK/DWP high time
VCLK/DWP low time
Mode transition time
Transmit-Only power up
time
Endurance
IH
T
OF
—
250
20 + .1
C
B
—
250
ns
100 pF
T
SP
—
50
50
ns
(Note 3)
T
WR
—
10
—
10
ms
Byte or Page mode
T
VAA
—
2000
—
1000
ns
T
T
T
T
VHIGH
4000
4700
—
0
—
—
500
—
600
1300
—
0
—
—
500
—
ns
ns
ns
ns
VLOW
VHZ
VPU
—
10M
—
10M
—
cycles
25
Mode (Note 4)
°
C, Vcc = 5.0V, Block
Note 1: Not 100% tested. C
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of START or STOP
conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
B
= total capacitance of one bus line in pF.
I
specification for standard operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LC512/S16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512/W16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND,WAFER - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512/WF16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512-E/MF | 功能描述:電可擦除可編程只讀存儲(chǔ)器 64kx8 - 2.5V RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC512-E/MS | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE, EXT - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC EEPROM 512KBIT 400KHZ 8MSOP 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE, EXT, 8 MSOP 3x3mm TUBE |
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