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參數(shù)資料
| 型號： | 24LC41 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 1K/4K 2.5V Dual Mode, Dual Port I 2 C Serial EEPROM |
| 中文描述： | 1K/4K 2.5V的雙模式，雙端口的I 2 C串行EEPROM |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | 24LC41 |
24LC41
DS21140B-page 4
1996 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
2.1
DDC Monitor Port
The DDC Monitor Port operates in two modes, the
Transmit-Only Mode and the bi-directional Mode. There
is a separate 2-wire protocol to support each mode,
each having a separate clock input and sharing a com-
mon data line (DSDA). The device enters the Transmit-
Only Mode upon power-up. In this mode, the device
transmits data bits on the DSDA pin in response to a
clock signal on the VCLK/DWP pin. The device will
remain in this mode until a valid high to low transition is
placed on the DSCL input. When a valid transition on
DSCL is recognized, the device will switch into the bi-
directional Mode. The only way to switch the device
back to the Transmit-Only Mode is to remove power
from the device.
2.1.1
TRANSMIT-ONLY MODE
The device will power up in the Transmit-Only Mode.
This mode supports a unidirectional 2-wire protocol for
transmission of the contents of the memory array. This
device requires that it be initialized prior to valid data
being sent in the Transmit-Only Mode (Section 2.1.2).
In this mode, data is transmitted on the DSDA pin in 8-
bit bytes, each followed by a ninth, null bit (Figure 2-1).
The clock source for the Transmit-Only Mode is pro-
vided on the VCLK/DWP pin, and a data bit is output on
the rising edge on this pin. The eight bits in each byte
are transmitted by most significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmitted,
the output will wrap around to the first location and con-
tinue. The bi-directional Mode Clock (DSCL) pin must
be held high for the device to remain in the Transmit-
Only Mode.
2.1.2
INITIALIZATION PROCEDURE
After V
mit-Only Mode. Nine clock cycles on the VCLK/DWP
pin must be given to the device for it to perform internal
sychronization. During this period, the DSDA pin will be
in a high impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the most significant bit of a byte.
The device will power up at an indeterminate byte
address (Figure 2-2).
CC
has stabilized, the device will be in the Trans-
FIGURE 2-1:
TRANSMIT-ONLY MODE
FIGURE 2-2:
DEVICE INITIALIZATION
DSCL
DSDA
VCLK/DWP
T
VAA
T
VAA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB)
Bit 7
T
VLOW
T
VHIGH
T
VAA
T
VAA
Bit 8
Bit 7
High Impedance for 9 clock cycles
T
VPU
1
2
8
9
10
11
SCL
SDA
VCLK/DWP
Vcc
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PDF描述 |
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| 24LC41-IP | 1K/4K 2.5V Dual Mode, Dual Port I 2 C Serial EEPROM |
| 24LC41-P | 1K/4K 2.5V Dual Mode, Dual Port I 2 C Serial EEPROM |
| 24LC61-IP | 1K/2K Software Addressable I 2 C ⑩ Serial EEPROM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LC512/S16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512/W16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND,WAFER - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512/WF16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512-E/MF | 功能描述:電可擦除可編程只讀存儲器 64kx8 - 2.5V RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC512-E/MS | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE, EXT - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC EEPROM 512KBIT 400KHZ 8MSOP 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE, EXT, 8 MSOP 3x3mm TUBE |
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