參數(shù)資料
型號: 24LC164
英文描述: 3.3V 64k x 40 NV SRAM SIMM
中文描述: 串行EEPROM
文件頁數(shù): 6/12頁
文件大?。?/td> 163K
代理商: 24LC164
1999 Microchip Technology Inc.
DS21101G-page 3
24LC174
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
Standard Mode
Vcc= 4.5 - 5.5V
Fast Mode
Units
Remarks
Min
Max
Min
Max
Clock frequency
FCLK
100
400
kHz
Clock high time
THIGH
4000
600
ns
Clock low time
TLOW
4700
1300
ns
SDA and SCL rise time
TR
1000
300
ns
(Note 1)
SDA and SCL fall time
TF
300
300
ns
(Note 1)
START condition hold time
THD:STA
4000
600
ns
After this period the rst clock
pulse is generated
START condition setup
time
TSU:STA
4700
600
ns
Only relevant for repeated
START condition
Data input hold time
THD:DAT
0—
0
ns
Data input setup time
TSU:DAT
250
100
ns
STOP condition setup time
TSU:STO
4000
600
ns
Output valid from clock
TAA
3500
900
ns
(Note 2)
Bus free time
TBUF
4700
1300
ns
Time the bus must be free
before a new transmission can
start
Output fall time from VIH
min to VIL max
TOF
250
20 +0.1
CB
250
ns
(Note 1), CB
≤ 100 pF
Input lter spike suppres-
sion (SDA and SCL pins)
TSP
50
50
ns
(Note 3)
Write cycle time
TWR
10
10
ms
Byte or Page mode
Endurance
1M
1M
cycles
25°C, Vcc = 5.0V, Block Mode
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undened region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specication for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specic appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
SCL
SDA
IN
SDA
OUT
TSU:STA
TSP
TAA
TF
TLOW
THIGH
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TBUF
TAA
TR
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