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參數(shù)資料
| 型號： | 24LC164 |
| 英文描述： | 3.3V 64k x 40 NV SRAM SIMM |
| 中文描述： | 串行EEPROM |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 163K |
| 代理商： | 24LC164 |
1999 Microchip Technology Inc.
DS21101G-page 7
24LC174
7.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address
read, random
read, and sequential read.
7.1
Current Address Read
The 24LC174 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W bit set to one, the 24LC174 issues an
acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer but does gen-
erate a stop condition and the 24LC174 discontinues
transmission (Figure 8-1).
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, rst the word address must
be set. This is done by sending the word address to the
24LC174 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LC174 will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC174 dis-
continues transmission (Figure 8-2).
7.3
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC174 transmits the
rst data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC174 to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads the 24LC174 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.
7.4
Noise Protection
The 24LC174 employs a Vcc threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and lter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
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| 24LC32AISN | I2C Serial EEPROM |
| 24LC32AP | I2C Serial EEPROM |
| 24LC32ASM | I2C Serial EEPROM |
| 24LC32ASN | I2C Serial EEPROM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LC164/P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24LC164-/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:16K 2.5V Cascadable I2C⑩ Serial EEPROM |
| 24LC164-/PQTP | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:16K 2.5V Cascadable I2C⑩ Serial EEPROM |
| 24LC164-/PSQTP | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:16K 2.5V Cascadable I2C⑩ Serial EEPROM |
| 24LC164/SN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
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