參數(shù)資料
型號(hào)： 24FC256
英文描述： 24AA256/LC256/FC256 Datasheet
中文描述： 24AA256/LC256/FC256數(shù)據(jù)表
文件頁(yè)數(shù)： 6/28頁(yè)
文件大小： 449K
代理商： 24FC256
24AA256/24LC256/24FC256
DS21203L-page 6
2003 Microchip Technology Inc.
4.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes
in the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high, determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line, while the clock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX256) will leave the data line high to enable
the master to generate the Stop condition.
Note:
The 24XX256 does not generate any
Acknowledge
bits
programming cycle is in progress.
if
an
internal
相關(guān)PDF資料
PDF描述
24FC32 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC32-IP 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC32-ISM 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC32-P 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC32-SM 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
24FC256/S15K 制造商:Microchip Technology Inc 功能描述:256K, 32K X 8, 2.5V HI-SPEED S - Gel-pak, waffle pack, wafer, diced wafer on film
24FC256/W15K 制造商:Microchip Technology Inc 功能描述:256K, 32K X 8, 2.5V HI-SPEED S - Gel-pak, waffle pack, wafer, diced wafer on film
24FC256/WF15K 制造商:Microchip Technology Inc 功能描述:256K, 32K X 8, 2.5V HI-SPEED S - Gel-pak, waffle pack, wafer, diced wafer on film
24FC256E/MF 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K I2C CMOS Serial EEPROM
24FC256-E/MF 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K I2C CMOS Serial EEPROM
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