參數(shù)資料
型號: 24FC256
英文描述: 24AA256/LC256/FC256 Datasheet
中文描述: 24AA256/LC256/FC256數(shù)據(jù)表
文件頁數(shù): 3/28頁
文件大?。?/td> 449K
代理商: 24FC256
2003 Microchip Technology Inc.
DS21203L-page 3
24AA256/24LC256/24FC256
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
Automotive (E):
V
CC
= +1.8V to 5.5V
V
CC
= +2.5V to 5.5V
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
1
F
CLK
Clock frequency
100
400
1000
1000
300
300
300
100
3500
900
400
kHz
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC256
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC256
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC256
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC256
All except, 24FC256
2.5V
V
CC
5.5V 24FC256
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC256
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC256
(Note 2)
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC256
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC256
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC256
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC256
1.8 V
V
CC
<
2.5V
2.5 V
V
CC
5.5V
2.5 V
V
CC
5.5V 24FC256
1.8V
V
CC
<
2.5V
2.5V
V
CC
5.5V
2.5V
V
CC
5.5V 24FC256
2
T
HIGH
Clock high time
4000
600
500
4700
1300
500
4000
600
250
4700
600
250
0
250
100
100
4000
600
250
4000
600
600
4700
1300
1300
4700
1300
500
ns
3
T
LOW
Clock low time
ns
4
T
R
SDA and SCL rise time
(Note 1)
ns
5
T
F
SDA and SCL fall time
(Note 1)
T
HD
:
STA
Start condition hold time
ns
6
ns
7
T
SU
:
STA
Start condition setup time
ns
8
9
T
HD
:
DAT
Data input hold time
T
SU
:
DAT
Data input setup time
ns
ns
10
T
SU
:
STO
Stop condition setup time
ns
11
T
SU
:
WP
WP setup time
ns
12
T
HD
:
WP
WP hold time
ns
13
T
AA
Output valid from clock
(Note 2)
ns
14
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
ns
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model, which can be obtained from Microchip’s web site:
www.microchip.com.
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24FC32 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
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參數(shù)描述
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