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參數(shù)資料
| 型號： | 24C256 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 256K IIC CMOS serial EEPROM(4.5~5.5V,256K位,100K擦寫周期,EEPROM) |
| 中文描述： | 256K進(jìn)口證的CMOS串行EEPROM（4.5?5.5V的，256K位，10萬擦寫周期和EEPROM） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 24C256 |
24AA256/24LC256/24C256
DS21203A-page 8
Preliminary
1997 Microchip Technology Inc.
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput.) Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition, followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
resent. If the cycle is complete, then the device will
return the ACK, and the master can then proceed with
the next read or write command. See Figure 7-1 for flow
diagram.
FIGURE 7-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)
Next
Operation
NO
YES
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