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參數(shù)資料
| 型號(hào)： | 24C256 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 256K IIC CMOS serial EEPROM(4.5~5.5V,256K位,100K擦寫周期,EEPROM) |
| 中文描述： | 256K進(jìn)口證的CMOS串行EEPROM（4.5?5.5V的，256K位，10萬擦寫周期和EEPROM） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 24C256 |
24AA256/24LC256/24C256
1997 Microchip Technology Inc.
Preliminary
DS21203A-page 3
TABLE 1-3
AC CHARACTERISTICS
All parameters apply across the spec-
ified operating ranges unless other-
wise noted
Commercial (C): V
CC
= +1.8V to 5.5V
Industrial (I):
V
CC
= +1.8V to 5.5V
Automotive (E): V
CC
= +4.5V to 5.5V
Tamb = 0
°
C to +70
°
C
Tamb = -40
°
C to +85
°
C
Tamb = -40
°
C to 125
°
C
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
F
CLK
—
—
—
100
100
400
—
—
—
—
—
—
1000
1000
300
300
300
300
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3500
3500
900
—
—
—
250
kHz
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
(Note 2)
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V (E Temp range)
1.8V
≤
V
CC
≤
2.5V
2.5V
≤
V
CC
≤
5.5V
C
B
≤
100 pF (Note 1)
Clock high time
T
HIGH
4000
4000
600
4700
4700
1300
—
—
—
—
—
—
4000
4000
600
4700
4700
600
0
250
250
100
4000
4000
600
4000
4000
600
4700
4700
1300
—
—
—
4700
4700
1300
20
ns
Clock low time
T
LOW
ns
SDA and SCL rise time
(Note 1)
T
R
ns
SDA and SCL fall time
(Note 1)
T
F
ns
START condition hold time
T
HD
:
STA
ns
START condition setup time
T
SU
:
STA
ns
Data input hold time
Data input setup time
T
HD
:
DAT
T
SU
:
DAT
ns
ns
STOP condition setup time
T
SU
:
STO
ns
WP setup time
T
SU
:
WP
ns
WP hold time
T
HD
:
WP
ns
Output valid from clock
(Note 2)
T
AA
ns
Bus free time: Time the bus must be
free before a new transmission can
start
Output fall time from Vih
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page)
T
BUF
ns
T
OF
ns
T
SP
—
50
ns
(Notes 1 and 3)
T
WC
—
5
10
—
ms
V
CC
≥
2.5V
V
CC
< 2.5V
25
°
C, V
CC
= 5.0V, Block Mode (Note 4)
Endurance
Note 1:
1M
cycles
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
The combined Tsp and Vhys specifications are due to new Schmitt trigger inputs which provide improved noise spike sup-
pression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.
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