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參數(shù)資料
| 型號： | 24C256 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 256K IIC CMOS serial EEPROM(4.5~5.5V,256K位,100K擦寫周期,EEPROM) |
| 中文描述： | 256K進(jìn)口證的CMOS串行EEPROM（4.5?5.5V的，256K位，10萬擦寫周期和EEPROM） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 24C256 |
24AA256/24LC256/24C256
1997 Microchip Technology Inc.
Preliminary
DS21203A-page 7
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the start condition from the master, the con-
trol code (four bits), the chip select (three bits), and the
R/W bit (which is a logic low) are clocked onto the bus
by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the high-order byte of the word
address and will be written into the address pointer of
the 24xx256. The next byte is the least significant
address byte. After receiving another acknowledge sig-
nal from the 24xx256, the master device will transmit
the data word to be written into the addressed memory
location. The 24xx256 acknowledges again and the
master generates a stop condition. This initiates the
internal write cycle, and, during this time, the 24xx256
will not generate acknowledge signals (Figure 6-1). If
an attempt is made to write to the array with the WP pin
held high, the device will acknowledge the command
but no write cycle will occur, no data will be written, and
the device will immediately accept a new command.
After a byte write command, the internal address
counter will point to the address location following the
one that was just written.
6.2
Page Write
The write control byte, word address, and the first data
byte are transmitted to the 24xx256 in the same way as
in a byte write. But instead of generating a stop condi-
tion, the master transmits up to 63 additional bytes,
which are temporarily stored in the on-chip page buffer
and will be written into memory after the master has
transmitted a stop condition. After receipt of each word,
the six lower address pointer bits are internally incre-
mented by one. If the master should transmit more than
64 bytes prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received, an inter-
nal write cycle will begin. (Figure 6-2). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command subject to
T
BUF
.
6.3
Write Protection
The WP pin allows the user to write-protect the entire
array (0000-7FFF) when the pin is tied to V
CC
. If tied to
V
SS
or left floating, the write protection is disabled. The
WP pin is sampled at the STOP bit for every write com-
mand (Figure 1-1) Toggling the WP pin after the STOP
bit will have no effect on the execution of the write cycle.
FIGURE 6-1:
BYTE WRITE
FIGURE 6-2:
PAGE WRITE
X
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
DATA
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
X = don’t care bit
S 1 0 1 0
0
A
2
A
1
A
0
P
X
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
DATA BYTE 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA BYTE 63
A
C
K
X = don’t care bit
S 1 0 1 0
0
A
2
A
1
A
0
P
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