參數(shù)資料
型號(hào): 24C04
廠商: 意法半導(dǎo)體
元件分類(lèi): EEPROM
英文描述: 4 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
中文描述: 4千位串行I2C總線的EEPROM與用戶(hù)定義的塊寫(xiě)保護(hù)
文件頁(yè)數(shù): 9/16頁(yè)
文件大小: 125K
代理商: 24C04
ory address bits (A7-A3) are the same inside one
block. The master sends from one up to 8 bytes of
data, which are each acknowledged by the mem-
ory. After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond
to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (t
W
) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
duced by an ACK polling sequence issued by the
master.
WRITE Cycle
in Progress
AI01099B
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YES
NO
ReSTART
STOP
Proceed
WRITE Operation
Proceed
Random Address
READ Operation
Send
Byte Address
First byte of instruction
with RW = 0 already
decoded by ST24xxx
Figure 8. Write Cycle Polling using ACK
AI00855B
1FFh
b7
b3 b2
X
X
100h
Block 1
Block 0
Protect Flag
Enable = 0
Disable = 1
8 byte
boundary
address
Protect Location
Figure 7. Memory Protection
9/16
ST24/25C04, ST24/25W04
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