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參數(shù)資料
| 型號： | 24C04 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | EEPROM |
| 英文描述： | 4 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection |
| 中文描述： | 4千位串行I2C總線的EEPROM與用戶定義的塊寫保護(hù) |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 125K |
| 代理商： | 24C04 |
Mode
RW bit
MODE
Bytes
Initial Sequence
Current Address Read
’1’
X
1
START, Device Select, RW = ’1’
Random Address Read
’0’
X
1
START, Device Select, RW = ’0’, Address,
’1’
reSTART, Device Select, RW = ’1’
’1’
X
1 to 512
Similar to Current or Random Mode
Byte Write
’0’
X
1
START, Device Select, RW = ’0’
Multibyte Write
(2)
’0’
V
IH
4
START, Device Select, RW = ’0’
Page Write
’0’
V
IL
8
START, Device Select, RW = ’0’
Notes:
1. X = V
or V
2. Multibyte Write not available in ST24/25W04 versions.
Table 4. Operating Modes
(1)
Device Code
Chip Enable
Block
Select
RW
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Device Select
1
0
1
0
E2
E1
A8
RW
Note:
The MSB b7 is sent first.
Table 3. Device Select Code
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: V
CC
lock out write protect.
In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V
CC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when V
CC
drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
CC
must be applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL).
The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V
CC
to act as a pull up (see Figure 3).
Serial Data (SDA).
The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V
CC
to act as pull up (see Figure 3).
Chip Enable (E1 - E2).
These chip enable inputs
are used to set the 2 least significant bits (b2, b3)
of the 7 bit device select code. These inputs may
be driven dynamically or tied to V
CC
or V
SS
to
establish the device select code.
Protect Enable (PRE).
The PRE input pin, in ad-
dition to the status of the Block Address Pointer bit
(b2, location 1FFh as in Figure 7), sets the PRE
write protection active.
Mode (MODE).
The MODE input is available on pin
7 (see also WC feature) and may be driven dynami-
cally. It must be at V
IL
or V
IH
for the Byte Write
mode, V
IH
for Multibyte Write mode or V
IL
for Page
Write mode. When unconnected, the MODE input
is internally read as V
IH
(Multibyte Write mode).
Write Control (WC).
An hardware Write Control
feature (WC) is offered only for ST24W04 and
ST25W04 versions on pin 7. This feature is usefull
to protect the contents of the memory from any
erroneous erase/write cycle. The Write Control sig-
nal is used to enable (WC = V
IH
) or disable (WC =
V
IL
) the internal write protection. When uncon-
nected, the WC input is internally read as V
IL
and
the memory area is not write protected.
3/16
ST24/25C04, ST24/25W04
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