參數(shù)資料
型號(hào): 24AA174
廠商: Microchip Technology Inc.
英文描述: 16K 1.8V Cascadable CMOS serial EEPROMs with OTP Security Page(16K位,1.8V層疊IIC串行EEPROM)
中文描述: 16K的1.8安全頁(yè)的OTP(16K的位,1.8層疊進(jìn)口證串行EEPROM的串行EEPROM級(jí)聯(lián)的CMOS)
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 127K
代理商: 24AA174
1995 Microchip Technology Inc.
DS21102C-page 5
24AA174
4.0
BUS CHARACTERISTICS
4.1
Device Addressing and Operation
A control byte is the first byte received following the
start condition from the master device. The first bit is
always a one. The next three bits of the control byte
are the device select bits (A2, A1, A0). They are used
to select which of the eight devices are to be accessed.
The A1 bit must be the inverse of the A1 device select
pin.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24AA174 looks for the
slave address for the device selected. Depending on
the state of the R/W bit, the 24AA174 will select a read
or write operation.
FIGURE 4-1:
CONTROL BYTE
ALLOCATION
Operation
Control Code
Block Select
R/W
Read
1
A2 A1 A0
Block Address
1
Write
1
A2 A1 A0
Block Address
0
START
READ/WRITE
SLAVE ADDRESS
R/W
1
A2
A1
A0
B2
B1
B0
A
MSB
LSB
5.0
WRITE OPERATION
5.1
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24AA174. After
receiving another acknowledge signal from the
24AA174 the master device will transmit the data word
to be written into the addressed memory location. The
24AA174 acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle, and during this time the 24AA174 will not gener-
ate acknowledge signals (see Figure 5-1).
5.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24AA174 in the same way
as in a byte write. But instead of generating a stop con-
dition the master transmits up to sixteen data bytes to
the 24AA174 which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than six-
teen words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (see Figure 8-1).
FIGURE 5-1:
BYTE WRITE
S
T
O
P
SDA LINE
P
DATA
S
T
A
R
T
CONTROL
BYTE
S
WORD
ADDRESS
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
A
C
K
A
C
K
A
C
K
1 A2
B0
A1 A0 B2 B1
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