參數(shù)資料
型號(hào): 24AA174
廠商: Microchip Technology Inc.
英文描述: 16K 1.8V Cascadable CMOS serial EEPROMs with OTP Security Page(16K位,1.8V層疊IIC串行EEPROM)
中文描述: 16K的1.8安全頁(yè)的OTP(16K的位,1.8層疊進(jìn)口證串行EEPROM的串行EEPROM級(jí)聯(lián)的CMOS)
文件頁(yè)數(shù): 3/10頁(yè)
文件大?。?/td> 127K
代理商: 24AA174
1995 Microchip Technology Inc.
DS21102C-page 3
24AA174
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
Standard Mode
V
CC
Fast Mode
= 4.5 - 5.5V
Units
Remarks
Min
Max
Min
Max
Clock frequency
F
CLK
100
400
kHz
Clock high time
T
HIGH
4000
600
ns
Clock low time
T
LOW
4700
1300
ns
SDA and SCL rise time
T
R
1000
300
ns
Note 2
SDA and SCL fall time
T
F
300
300
ns
Note 2
START condition hold time
T
HD
:
STA
4000
600
ns
After this period the first
clock pulse is generated
START condition setup
time
T
SU
:
STA
4700
600
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
0
ns
Data input setup time
T
SU
:
DAT
250
100
ns
STOP condition setup time
T
SU
:
STO
4000
600
ns
Output valid from clock
T
AA
3500
900
ns
Note 1
Bus free time
T
BUF
4700
1300
ns
Time the bus must be free
before a new transmission
can start
Output fall time from
V
IH
min to V
IL
max
T
OF
250
20 +0.1
C
B
250
ns
Note 2, C
B
100 pF
Input filter spike suppres-
sion (SDA and SCL pins)
T
SP
50
50
ns
Note 3
Write cycle time
T
WR
10
10
ms
Byte or Page mode
Endurance
100,000
100,000
E/W
Cycles
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2: Not 100% tested. C
B
= total capacitance of one bus line in pF.
Note 3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
SU:STA
t
HD:STA
t
F
t
LOW
t
HIGH
t
R
t
SU:STO
t
BUF
t
t
AA
t
SDA
OUT
SDA
IN
SCL
HD:DAT
t
SU:DAT
t
AA
SP
t
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