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參數(shù)資料
| 型號(hào)： | 24AA174 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 16K 1.8V Cascadable CMOS serial EEPROMs with OTP Security Page(16K位,1.8V層疊IIC串行EEPROM) |
| 中文描述： | 16K的1.8安全頁(yè)的OTP（16K的位，1.8層疊進(jìn)口證串行EEPROM的串行EEPROM級(jí)聯(lián)的CMOS） |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大小： | 127K |
| 代理商： | 24AA174 |
24AA174
DS21102C-page 4
1995 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24AA174 supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions, while the 24AA174
works as slave. Both, master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
3.0
BUS CHARACTERISTICS
The following
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 3-1).
bus protocol
has been defined:
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end
of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the
slave. In this case, the slave (24AA174) will leave the
data line HIGH to enable the master to generate the
STOP condition.
Note:
The 24AA174 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
(A)
(B)
(D)
(D)
(C)
(A)
START CONDITION
ADDRESS
OR
ACKNOWLEDGE
VALID
DATA ALLOWED
TO CHANGE
STOP
CONDITION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24AA174/P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24AA174-/P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:16K 1.8V Cascadable I2C⑩ Serial EEPROM with OTP Security Page |
| 24AA174/SN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| 24AA174-/SN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:16K 1.8V Cascadable I2C⑩ Serial EEPROM with OTP Security Page |
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