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參數(shù)資料
| 型號： | 22152 |
| 元件分類： | SRAM |
| 英文描述： | 64K Nonvolatile SRAM |
| 中文描述： | 使用AMD的設備運行狀態(tài)位 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 127K |
| 代理商： | 22152 |
July 24, 2002
Using the Operation Status Bits in AMD Devices
5
S U P P L E M E N T
AMD Flash devices provide the DQ3 Status Bit to
enable the system to check if the Sector Erase time-
out window is open before every Sector Erase co-
mand cycle is issued.
Check DQ3:
If the Sector Erase time-out window is open,
DQ3 will be a
“
0
”
. When the 50 μs time-out has
expired, DQ3 will be set to a
“
1
”
which indicates
that the Sector Erase operation has begun. Any
attempt to write additional commands will be ig-
nored until the ongoing Sector Erase operation
is completed. To ensure that multiple Sector
Erase commands have been accepted, the sys-
tem software should check the status of DQ3
prior to and following each Sector Erase com-
mand cycle. Refer to Figure 7 for the polling se-
quence.The first check (prior to the Sector Erase
cycle) is to ensure that the time-out window is
still open and the second check (following the
Sector Erase cycle) is to ensure that the com-
mand has been accepted. If DQ3 is a
“
1
”
on the
second status check, it indicates that the 50us
time-out has expired and that last sector erase
command was not accepted.
7. Checking if the Write-to-Buffer Abort condition has
been initiated. The DQ1 Status Bit indicates
whether a Write-to-Buffer operation is in progress or
has been aborted.
Polling DQ1:
If a Write-to-Buffer operation is in progress or
has not been used, the DQ1 status Bit will be a
“
0
”
. When a Write-to-Buffer operation is aborted,
DQ1 will be set to
“
1
”
to indicated the Write-to-
Buffer Abort condition has been initiated.
IMPLEMENTATION ISSUES
The following points must be noted when implementing
the various polling algorithms discussed above:
1. To determine if DQ6 or DQ2 is toggling the CPU
must:
a. Read DQ0-DQ7
b. Store DQ2/DQ6
c. Read DQ0-DQ7 again
d. Compare current DQ2/DQ6 value with that
stored in step (b).
2. DQ5
The DQ5 Status Bit
must
be checked in conjunction
with the DQ6 or DQ7 Status Bits when polling the
Flash device for Program/Erase completion. See
Figures 3, 4, 5 and 6.
3. The internal state machine runs asynchronously to
the system CPU. The internal switching of the MUX
is not synchronized with system CPU access. How-
ever, the next Read cycle will output valid data on
DQ0-DQ7. Whenever the status appears to indicate
that DQ5 is active, the status must be checked
again to ensure that the error is valid and not a re-
sult of reading during the transition form valid status
to valid data.
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