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| 型號(hào)： | 22152 |
| 元件分類： | SRAM |
| 英文描述： | 64K Nonvolatile SRAM |
| 中文描述： | 使用AMD的設(shè)備運(yùn)行狀態(tài)位 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 127K |
| 代理商： | 22152 |
.
Publication#
22152
Issue Date:
July 24, 2002
Rev:
D
Amendment/
0
Using the Operation Status Bits in AMD
Devices
Application Note
First generation Flash memory devices required the
system CPU to execute the program and erase algo-
rithms in software. These algorithms consisted of a
complex series of operations with strict timing require-
ments in order to set-up, control and monitor the Flash
device. Erroneous execution of these algorithms could
render the Flash device inoperable thereby compro-
mising system reliability. To eliminate concerns by
system software designers AMD choose to embed the
algorithms within the Flash device.
WHY ARE THE OPERATION STATUS BITS
PROVIDED
From the system point of view the Flash memory de-
vice functions both as a memory and as a peripheral to
the CPU. Operation as a memory device is straight for-
ward. Operation as a peripheral involves following a
command and status protocol similar to other system
peripherals. The protocol consist of JEDEC compliant
command sequences which are written to the device
followed by status interrogation read from the device.
Through this protocol the system CPU communicates
with a sophisticated state machine internal to the Flash
memory device. All AMD Flash devices therefore pro-
vide Operation Status Bits to monitor the status of
these embedded operations.
WHAT CAN BE DETERMINED FROM
THESE STATUS BITS
The following information can be determined by polling
the Operation Status Bits:
1. Program cycle completion
2. Chip Erase cycle completion
3. Sector Erase cycle completion
4. Checking if a Sector is in the Erase Suspend Mode
5. Ensuring that the Program/Erase operation has
completed successfully
6. Checking if the Sector Erase time-out window is open
(when issuing multiple Sector Erase commands).
7. Checking if the Write-to-Buffer Abort condition has
been initiated.
WHAT ARE THE STATUS BITS PROVIDED
ON AMD FLASH DEVICES
The following Operation Status Bits are provided in the
status register of AMD Flash devices:
DQ7: Data# Polling
DQ6: Toggle Bit 1
DQ5: Exceeded Timing Limits Bit
DQ4: Reserved
DQ3: Sector Erase Timer Bit
DQ2: Toggle Bit 2 (not offered on all devices)
DQ1: Write-to-Buffer Abort
DQ0: Reserved
In addition to the Operation Status Bits, a Ready/Busy#
(RY/BY#) pin is also provided on
most
AMD Flash de-
vices. Checking the RY/BY# pin is another method by
which the host system can determine if the Flash de-
vice has completed a Program or Erase operation. This
document also discusses usage of the RY/BY# pin as
an alternative to polling the Operation Status Bits wher-
ever applicable.
HOW DO THE STATUS BITS ACTUALLY
WORK
Internally, AMD Flash devices multiplex the Data pins
(DQ0-DQ7) between the memory array and the Status
Register (see Figure 1). When a Program or Erase op-
eration begins, the multiplexer switches the Data pins
Status Register in 16-bit mode (BTYE# pin driven high)
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DQ7
DQ
6
D
Q5
D
Q4
D
Q3
DQ2
D
Q1
D
Q0
STATUS REGISTER
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Status Register in 8-bit mode (BTYE# pin driven low)
15
8
7
0
7
0
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