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參數(shù)資料
| 型號： | 141540 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Monitor On-Screen Display CMOS |
| 中文描述： | 顯示器屏幕顯示的CMOS |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 186K |
| 代理商： | 141540 |
MC141540
3
MOTOROLA
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to VSS
Symbol
Characteristic
Value
Unit
VDD
Vin
Supply Voltage
– 0.3 to + 7.0
V
Input Voltage
VSS – 0.3 to
VDD + 0.3
V
Id
Current Drain per Pin Excluding VDD
and VSS
25
mA
Ta
Tstg
Operating Temperature Range
0 to 85
°
C
Storage Temperature Range
– 65 to + 150
°
C
NOTE: Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteris-
tics tables or Pin Description section.
AC ELECTRICAL CHARACTERISTICS
(VDD = VDD(A) = 5.0 V, VSS = VSS(A) = 0 V, TA = 25
°
C, Voltage Referenced to VSS)
Symbol
Characteristic
Min
Typ
Max
Unit
tr
tf
Output Signal (R, G, B, FBKG and HTONE) Cload = 30 pF, see Figure 1
Rise Time
Fall Time
—
—
—
—
10
10
ns
ns
FHFLB
HFLB Input Frequency
—
—
100
kHz
DC CHARACTERISTICS
VDD = VDD(A) = 5.0 V
±
10%, VSS = VSS(A) = 0 V, TA = 25
°
C, Voltage Referenced to VSS
Symbol
Characteristic
Min
Typ
Max
Unit
VOH
High Level Output Voltage
Iout = – 5 mA
VDD – 0.8
—
—
V
VOL
Low Level Output Voltage
Iout = 5 mA
—
—
VSS + 0.4
V
VIL
VIH
Digital Input Voltage (Not Including SDA and SCL)
Logic Low
Logic High
—
0.7 VDD
—
—
0.3 VDD
—
V
V
VIL
VIH
Input Voltage of Pin SDA and SCL in SPI Mode
Logic Low
Logic High
—
0.7 VDD
—
—
0.3 VDD
—
V
V
III
III
High–Z Leakage Current (R, G, B and FBKG)
– 10
—
+ 10
μ
A
Input Current (Not Including RP, VCO, R, G, B, FBKG and HTONE)
– 10
—
+ 10
μ
A
IDD
Supply Current (No Load on Any Output)
—
9*
—
mA
* Not a guaranteed limit.
90%
10%
90%
10%
tf
tr
Figure 1. Switching Characteristics
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tions of any voltage higher than the maximum
rated voltages to this high impedance circuit.
For proper operation it is recommended that
Vin and Vout be constrained to the range VSS
≤
(Vin or Vout)
≤
VDD. Unused inputs must always
be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left
open.
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