參數(shù)資料
型號(hào): 0W344-005-XTP
廠商: ON Semiconductor
文件頁(yè)數(shù): 8/43頁(yè)
文件大?。?/td> 0K
描述: DSP BELASIGNA 200 AUDIO 52-NQFN
產(chǎn)品變化通告: BelaSigna 200 QFN Obsolescence 09/Dec/2009
標(biāo)準(zhǔn)包裝: 1,000
系列: BelaSigna® 200
類(lèi)型: 音頻處理器
應(yīng)用: 便攜式設(shè)備
安裝類(lèi)型: 表面貼裝
封裝/外殼: 52-TFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 52-NQFP(8x8)
包裝: 帶卷 (TR)
BelaSigna 200
6.0 Architecture Overview
6.1 RCore DSP
The RCore is a 16-bit fixed-point, dual-Harvard-architecture DSP. It includes efficient normalize and de-normalize instructions, plus
support for double-precision operations to provide the additional dynamic range needed for many applications. All memory locations in
the system are accessible by the RCore using several addressing modes including indirect and circular modes. The RCore generally
assumes master functionality of the system.
6.1.1. RCore DSP Architecture
Figure 9: RCore Programming Model
AH
X
MU
PH
PL
ST
ALU
EXP
AE
AL
Limiter
Barrel
Shifter
IMM/SIMM
PC
Y
01
P
LC
RE
PCU
CTRL
Internal Router
XRAM
YRAM
X_AGU
PCFG0
PCFG1
PCFG2
R0
R1
R2
R3
Y_AGU
PCFG4
PCFG5
PCFG6
R4
R5
R6
R7
Y_Bus
X_Bus
PRAM
P_Bus
D_SYS_CTRL
D_INT_EBL
D_AUX_REG0
D_AUX_REG4
EXT3
D_INT_STATUS
DCU
Data registers
The RCore is a single-cycle pipelined multiply-accumulate (MAC) architecture that feeds into a 40-bit accumulator complete with barrel
shifter for fast normalization and de-normalization operations. Program execution is controlled by a sequencer that employs a three-
stage pipeline (FETCH, DECODE, EXECUTE). Furthermore, the RCore incorporates pointer configuration registers for low cycle-count
address generation when accessing the three memories: program memory (PRAM), X data memory (XRAM) and Y data memory
(YRAM).
Rev. 16 | Page 16 of 43 | www.onsemi.com
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