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| 型號： | 0W344-005-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 18/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | DSP BELASIGNA 200 AUDIO 52-NQFN |
| 產品變化通告： | BelaSigna 200 QFN Obsolescence 09/Dec/2009 |
| 標準包裝： | 1,000 |
| 系列： | BelaSigna® 200 |
| 類型： | 音頻處理器 |
| 應用： | 便攜式設備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-TFQFN 裸露焊盤 |
| 供應商設備封裝： | 52-NQFP（8x8） |
| 包裝： | 帶卷 (TR) |
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BelaSigna 200
Two analog outputs designed to drive external amplifiers are also available.
Figure 13: Output Stage
8.3 Clock-Generation Circuitry
BelaSigna 200 operates with two main clock domains: a domain running on the system clock (SYS_CLK) and a domain running on the
main clock (MCLK). SYS_CLK can either be internally generated or externally delivered. It is used to drive all on-chip processors such
as the RCore, the WOLA coprocessor and the IOP. MCLK is generated by division of SYS_CLK and is used to drive all A/D converters,
D/A converters and external interfaces (except SPI, PCM, I
2S, and GPIO interfaces). The division factor used to create the desired
MCLK from SYS_CLK is configurable to support external clocks with a wide range of frequencies.
The sampling frequency of all A/D converters and D/A converters also depends on MCLK. When MCLK is 1.28MHz, sampling
frequencies in the interval 10.7kHz to 20kHz can be selected. Sampling frequencies up to 60kHz can be obtained with other MCLK
frequencies.
8.4 Battery Monitor
A programmable on-chip battery monitor is available for power management. The battery monitor works by incrementing a counter
value every time the battery voltage goes below a desired, configurable threshold value. This counter value can be used in an
application-specific power-management algorithm running on the RCore. The RCore can initiate any desired actions in case the battery
hits a predetermined value.
8.5 Multi-Chip Sample Clock Synchronization
BelaSigna 200 allows MCLK synchronization between two or more BelaSigna 200 chips connected in a multi-chip configuration.
Samples on multiple chips occur at the same instant in time. This is useful in applications using microphone arrays where synchronous
sampling is required. The sample clock synchronization is enabled using a control bit and a GPIO assignment that brings all MCLKs
across chips to zero phase at the same instant in time.
Rev. 16 | Page 25 of 43 | www.onsemi.com
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| 0W588-002-XUA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC BELASIGNA 200 WLCSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| 0W589-005-XDS | 功能描述:音頻模/數(shù)轉換器 IC AUDIO AD/DA RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
| 0W589-007-XDS | 功能描述:音頻模/數(shù)轉換器 IC AUDIO AD/DA RoHS:否 制造商:Wolfson Microelectronics 轉換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝: |
| 0W598001EVK | 制造商:ON Semiconductor 功能描述:B250 EDK SGL PURCH - Bulk |
| 0W633-001-XTP | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC BELASIGNA 250 CABGA 5X5 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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