參數(shù)資料
型號: 0W344-005-XTP
廠商: ON Semiconductor
文件頁數(shù): 42/43頁
文件大?。?/td> 0K
描述: DSP BELASIGNA 200 AUDIO 52-NQFN
產(chǎn)品變化通告: BelaSigna 200 QFN Obsolescence 09/Dec/2009
標(biāo)準(zhǔn)包裝: 1,000
系列: BelaSigna® 200
類型: 音頻處理器
應(yīng)用: 便攜式設(shè)備
安裝類型: 表面貼裝
封裝/外殼: 52-TFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 52-NQFP(8x8)
包裝: 帶卷 (TR)
BelaSigna 200
4.1.2. QFN Pad Out
Pad #
Pad Name
Pad Function
I/O
U/D
1
CAP0
Charge pump capacitor pin 0
N/A
2
VDBL
Double voltage
O
N/A
3
A|0
Audio signal input to ADC0
I
N/A
4
A|1/LOUT
Audio signal input to ADC0/line level output signal from preamp 0
I/O
N/A
5
A|R
Reference voltage for microphone
N/A
6
A|2
Audio signal input to ADC1
I
N/A
7
A|3
Audio signal input to ADC1
I
N/A
8
VREG
Regulated voltage for microphone bias
O
N/A
9
AGND
Analog ground
N/A
10
AI_RC
Remote control input
I
N/A
11
AOR
Reference voltage for DAC
N/A
12
AO1/RCVR1-
Audio signal output from DAC1/output from direct digital drive 1-
O
N/A
13
AO0/RCVR1+
Audio signal output from DAC0/output from direct digital drive 1+
O
N/A
Pad #
Pad Name
Pad Function
I/O
U/D
14
VBAT
Positive power supply
I
N/A
15
RCVR0-
Output from direct digital drive 0
O
N/A
16
RCVR0+
Output from direct digital drive 0
O
N/A
17
RCVRGND
Receiver return current
N/A
18
GPIO[3]/
NCLK_DIV_RESET/I2S_FA
General-purpose I/O/clock divider reset/I2S interface
analog blocks frame output
I/O
U
19
GPIO[2]/I2S_INA
General-purpose I/O/I2S interface analog blocks input
I/O
U
20
GPIO[1]/I2S_IND
General-purpose I/O/I2S interface analog blocks input
I/O
U
21
GPIO[0]/I2S_FD
General-purpose I/O/I2S interface digital blocks frame
I/O
U
22
VDDO
Digital pads supply input
I
N/A
23
GNDO
Digital pads ground
N/A
24
EXT_CLK
External clock input/internal clock output
I/O
U
25
DEBUG_RX
Debug port receive
I
U
26
DEBUG_TX
Debut port transmit
O
U
Pad #
Pad Name
Pad Function
I/O
U/D
27
RESERVED
N/A
28
TWSS_SDA
TWSS data
I/O
U
29
TWSS_CLK
TWSS clock
I
U
30
GNDC
Core logic ground
N/A
31
VDDC
Core logic, EEPROM and pad supply output
O
N/A
32
SPI_SERO
Serial peripheral interface serial data out
I/O
D
33
SPI_SERI
Serial peripheral interface serial data in
I
U
34
SPI_CS
Serial peripheral interface chip select
I/O
D
35
SPI_CLK
Serial peripheral interface clock
I/O
N/A
36
GPIO[15]
General-purpose I/O
I/O
U
37
GPIO[14]/PCM_FRAME
General-purpose I/O/PCM interface frame
I/O
U
38
GPIO[13]/PCM_OUT
General-purpose I/O/PCM interface output
I/O
U
39
GPIO[12]/PCM_IN
General-purpose I/O/PCM interface input
I/O
U
Pad #
Pad Name
Pad Function
I/O
U/D
40
N/C
No connection
N/A
41
N/C
No connection
N/A
42
GPIO[11]/PCM_CLK
General-purpose I/O/PCM interface clock
I/O
U
43
GNDO
Digital pads ground
N/A
44
VDDO
Digital pads supply input
I
N/A
45
GPIO[10]/DCLK
General-purpose I/O/class D receiver clock
I/O
U
46
LSAD[5]/GPIO[9]/UART_RX
Low-speed A/D/general-purpose I/O/general-purpose
UART receive
I/O
U
47
LSAD[4]/GPIO[8]/UART_TX
Low-speed A/D input/general-purpose I/O/general-
purpose UART transmit
I/O
U
48
LSAD[3]/GPIO[7]
Low-speed A/D input/general purpose I/P
I/O
U
49
LSAD[2]/GPIO[6]
Low-speed A/D input/general purpose I/P
I/O
U
50
LSAD[1]/GPIO[5]/I2S_OUTA
Low-speed A/D inputs/general-purpose I/O/I2S interface
analog blocks output
I/O
U
51
LSAD[0]/GPIO[4]/I2S_OUTD
Low-speed A/D inputs/general-purpose I/O/I2S interface
analog blocks output
I/O
U
52
CAP1
Charge pump capacitor pin 1
N/A
Rev. 16 | Page 8 of 43 | www.onsemi.com
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