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CHAPTER 11 WATCHDOG TIMER
11.4.2 Operation as interval timer
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0, the watchdog timer also operates
as an interval timer that repeatedly generates an interrupt request at time intervals specified by a count value set
in advance.
Bits 0 through 2 (TCL20 through TCL22) of the timer clock select register 2 (TCL2) can be used to select a count
clock (interval time). When bit 7 (RUN) of WDTM is set to 1, the watchdog timer starts operating as an interval timer.
In the interval timer mode, the interrupt mask flag (TMMK4) and priority specification flag (TMPR4) are valid, and
a maskable interrupt request (INTWDT) can be generated. The default priority of INTWDT is set the highest of all
the maskable interrupt requests.
The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set bit 7 of
WDTM (RUN) to 1 before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.
Cautions: 1. Once bit 4 (WDTM4) of WDTM has been set to 1 (when the watchdog timer mode is
selected), the interval timer mode is not set, unless the RESET signal is input.
2. The interval time immediately after it has been set by WDTM may be up to 0.5% shorter
than the set time.
3. The watchdog timer stops its counting operation when the subsystem clock is selected
as the CPU clock.
Table 11-5. Interval Time of Interval Timer
TCL22
TCL21
TCL20
Interval Time
At f
X
= 10.0 MHz
0
0
0
2
12
×
1/f
X
409.6
μ
s
0
0
1
2
13
×
1/f
X
819.2
μ
s
0
1
0
2
14
×
1/f
X
1.64 ms
0
1
1
2
15
×
1/f
X
3.28 ms
1
0
0
2
16
×
1/f
X
6.55 ms
1
0
1
2
17
×
1/f
X
13.1 ms
1
1
0
2
18
×
1/f
X
26.2 ms
1
1
1
2
20
×
1/f
X
104.9 ms
Remarks
1.
f
X
2.
TCL20-TCL22: Bits 0 through 2 of timer clock select register 2 (TCL2)
: Main system clock oscillation frequency