171
CHAPTER 7 CLOCK GENERATION CIRCUIT
V
DD
RESET
Interrupt request signal
System clock
CPU clock
Wait (26.2 ms: at 10.0 MHz operation)
Internal reset operation
Slowest
operation
Fastest
operation
Subsystem clock
operation
f
X
f
X
f
XT
f
X
High-speed
operation
7.6.2 Switching between system clock and CPU clock
The following figure illustrates how the system clock is switched to the CPU clock or vice versa.
Figure 7-8. Switching between System Clock and CPU Clock
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the time
during which oscillation stabilizes (2
18
/f
X
) is automatically secured.
After that, the CPU starts instruction execution at the slowest speed of the main system clock (6.4
μ
s: at
10.0 MHz operation).
<2> After the time during which the V
DD
voltage rises to the level at which the CPU can operate at the highest
speed has elapsed, processor clock control register (PCC) is rewritten so that the highest speed can be
selected.
<3> A drop of the V
DD
voltage is detected by using an interrupt request signal. If this happens, the subsystem
clock is selected (at this time, the subsystem clock must be in the oscillation stabilization status).
<4> The recovery of V
DD
voltage to the original level is detected by using an interrupt, 0 is set to bit 7 of PCC
(MCC), and oscillation of the main system clock is started. After the time required for oscillation to stabilize
has elapsed, PCC is rewritten, so that the highest speed can be selected.
Caution To select the main system clock again when the system operates on the subsystem clock with
the main system clock stopped, be sure to secure the oscillation stabilization time by program,
and then select the main system clock.