參數(shù)資料
型號: μPD30210
廠商: NEC Corp.
英文描述: 64-Bit MIPS RISC Microprocessor(64位MIPS RISC 微處理器)
中文描述: 64位MIPS RISC微處理器(64位的MIPS的RISC微處理器)
文件頁數(shù): 8/24頁
文件大?。?/td> 170K
代理商: ΜPD30210
μ
PD30200, 30210
8
Data Sheet U10116EJ6V0DS00
Pin Name
I/O
Function
JTDO
Output
JTAG data output.
Output of JTAG serial data.
JTMS
Input
JTAG command.
Indicates that input serial data is command data.
JTCK
Input
JTAG clock input.
Input of JTAG serial clock. If the JTAG interface is not used, set it to low level.
DivMode
Input
Mode setting.
Sets frequency ratio of MasterClock, TClock, and PClock.
DivMode (1:0) (V
R
4300)
Example
DivMode (1:0)
00
01
10
11
MasterClock
33.3 MHz
66.7 MHz
50.0 MHz
33.3 MHz
PClock
133 MHz
100.0 MHz
100.0 MHz
100.0 MHz
TClock
33.3 MHz
66.7 MHz
50.0 MHz
33.3 MHz
Ratio
1:4:1
2:3:2
1:2:1
1:3:1
Note 1
Note 2
Notes 1.
This setting is allowed with the 133 MHz model only. With the 100 MHz model,
this setting is reserved.
2.
This setting is allowed with the 100 MHz model only. With the 133 MHz model,
this setting is reserved.
DivMode (1:0) (V
R
4305)
Example
DivMode (1:0)
00
01
10
11
MasterClock
66.7 MHz
40 MHz
20 MHz
PClock
66.7 MHz
80 MHz
60 MHz
TClock
66.7 MHz
40 MHz
20 MHz
Ratio
1:1:1
Reserved
1:2:1
1:3:1
DivMode (2:0) (V
R
4310)
Example
DivMode (2:0)
000
001
010
011
100
101
110
111
MasterClock
26.7 MHz
22.2 MHz
66.7 MHz
33.3 MHz
33.3 MHz
50.0 MHz
33.3 MHz
PClock
133 MHz
133 MHz
167 MHz
100 MHz
133 MHz
100 MHz
100 MHz
TClock
26.7 MHz
22.2 MHz
66.7 MHz
33.3 MHz
33.3 MHz
50.0 MHz
33.3 MHz
Ratio
1:5:1
1:6:1
2:5:2
1:3:1
1:4:1
Reserved
1:2:1
1:3:1
Note
Note
This setting is allowed with the 167 MHz model only. With the 133 MHz model, this
setting is reserved.
After power application, do not change the value of these pins; otherwise the operation
is not guaranteed.
PLLCap (1:0)
PLL capacitor.
Connect capacitor to adjust internal PLL.
V
DD
P
PLL V
DD
.
Power supply for internal PLL.
GNDP
PLL GND.
Ground for internal PLL.
V
DD
Positive power supply pin.
GND
Ground pin.
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