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參數(shù)資料
| 型號： | μPD30210 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit MIPS RISC Microprocessor(64位MIPS RISC 微處理器) |
| 中文描述： | 64位MIPS RISC微處理器（64位的MIPS的RISC微處理器） |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 170K |
| 代理商： | ΜPD30210 |
μ
PD30200, 30210
10
Data Sheet U10116EJ6V0DS00
Capacitance (T
A
= 25
°
C, V
DD
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Input capacitance
C
In
f
C
= 1 MHz
10
pF
Output capacitance
C
out
Unmeasured pins returned to 0 V.
10
pF
AC Characteristics (T
C
= 0 to +85
°
C, V
DD
= 3.3
±
0.3 V):
(T
C
= 0 to +85
°
C, V
DD
= 3.0 to 3.5 V):
μ
PD30200-133, 30210-
×××
μ
PD30200-80, 30200-100
Clock Parameters
(1)
μ
PD30200-
×××
Parameter
Symbol
Conditions
μ
PD30200-80
μ
PD30200-100
μ
PD30200-133
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Master clock high-level width
t
MCkHigh
3.5
3.5
3.5
ns
Master clock low-level width
t
MCkLow
3.5
3.5
3.5
ns
Master clock frequency
Note
DivMode = 1:1
20
66.7
–
–
–
–
MHz
DivMode = 1:2
20
66.7
20
66.7
34
66.7
MHz
DivMode = 2:3
–
–
20
66.7
–
–
MHz
DivMode = 1:3
20
66.7
20
66.7
24
66.7
MHz
DivMode = 1:4
–
–
–
–
20
66.7
MHz
Master clock cycle
t
MCkP
DivMode = 1:1
15
50
–
–
–
–
ns
DivMode = 1:2
15
50
15
50
15
29
ns
DivMode = 2:3
–
–
15
50
–
–
ns
DivMode = 1:3
15
50
15
50
15
41
ns
DivMode = 1:4
–
–
–
–
15
50
ns
Clock jitter
t
MCJitter
±
500
±
500
±
500
ps
Master clock rise time
t
MCRise
4.0
4.0
4.0
ns
Master clock fall time
t
MCFall
4.0
4.0
4.0
ns
JTAG clock cycle
t
JTAGCkP
4
×
t
MCkP
4
×
t
MCkP
4
×
t
MCkP
ns
Note
The operation of the internal PLL of the
μ
PD30200-
×××
is guaranteed. The RP mode is supported only
by
μ
PD30200-80 and 30200-100 and guaranteed when the master clock frequency is 40 MHz or higher.
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