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參數(shù)資料
| 型號： | μPD30210 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-Bit MIPS RISC Microprocessor(64位MIPS RISC 微處理器) |
| 中文描述： | 64位MIPS RISC微處理器（64位的MIPS的RISC微處理器） |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 170K |
| 代理商： | ΜPD30210 |
μ
PD30200, 30210
7
Data Sheet U10116EJ6V0DS00
1. PIN FUNCTIONS
Pin Name
I/O
Function
SysAD (31:0)
I/O
System address/data bus.
32-bit bus for communication between processor and external agent.
SysCmd (4:0)
I/O
System command/data ID bus.
5-bit bus for communication of commands and data identifiers between processor
and external agent.
EValid
Input
External valid.
Signal indicating that external agent has transmitted valid address or data onto
SysAD bus and valid command or data identifier onto SysCmd bus.
PValid
Output
Processor valid.
Signal indicating that processor has transmitted valid address or data onto SysAD
bus and valid command or data identifier onto SysCmd bus.
EReq
Input
External request.
Signal used by external agent to request use of system interface.
PReq
Output
Processor request.
Signal used by processor to request use of system interface. If the processor detects a
protocol error, this signal oscillates with the same frequency as SClock (internal), and the
system interface hangs up.
PMaster
Output
Processor master.
Signal indicating processor controls system interface.
EOK
Input
External OK.
Signal indicating that external agent can accept processor request.
Int (4:0)
Input
Interrupt.
General-purpose processor interrupt requests, the input status of which can be confirmed
by bits 14 through 10 of cause register.
NMI
Input
Non-maskable interrupt.
Interrupt request that cannot be masked.
ColdReset
Input
Cold reset.
Signal that initializes internal status of processor. It can be made active/inactive without
synchronizing with the MasterClock.
Reset
Input
Reset.
Signal that generates reset exception without initializing internal status of processor.
MasterClock
Input
Master clock.
Clock input signal to processor.
TClock
Output
Transmit-receive signal clock
This is the basic clock for the system interface and is synchronized with the MasterClock.
SyncOut
Output
Synchronization clock output.
Output of synchronization clock.
SyncIn
Input
Synchronization clock input.
Input of synchronization clock.
JTDI
Input
JTAG data input.
Input of JTAG serial data.
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