參數(shù)資料
型號(hào): μPD30122
廠(chǎng)商: NEC Corp.
英文描述: 64-Bit RISC Microprosessor(64位RISC微處理器)
中文描述: 64位RISC Microprosessor(64位的RISC微處理器)
文件頁(yè)數(shù): 3/4頁(yè)
文件大小: 76K
代理商: ΜPD30122
EXAMPLE HANDHELD PC APPLICATION WITH THE V
RC
4173 COMPANION CHIP
V
R
4122
V
RC
4173
Line
Codec
DAA
IrLED
232
Driver
Touch
Panel
LCD Panel
32-bit
PC Connection
Port Control
PCM Audio
Scan Keyboard
SDRAM
ROM
PCM
D/A
Converter
PC Card
Control
Key
Scanner
CODEC
Interface
A/D
Converter
Touch
Panel
Control
Interval
Timer
/RTC
Interrupt
Control
Power
Management
VR4120
CPU
Core
Memory
Control
GPIO
/LED
PCI
Interface
DMA
Control
Serial
Interface
LCD
Control/
Graphics
Accelerator
PC
Card
Battery
V
R
4 1 0 0 F A M I LY C O M P A R I S O N
V
R
4111
V
R
4110
70 MHz
Instruction: 16 KB
Data: 8 KB
85 Dhrystone MIPS
MIPS I, II, III, MIPS16
Single-cycle,16-bit
2.5 V (core); 3.3 V (I/O)
Subset of ISA
64 MB DRAM
64 MB ROM
185 mW
224-pin FPBGA
10~70
o
C
0.25-micron UC2 process
V
R
4121
V
R
4120
168 MHz
Instruction: 16 KB
Data: 8 KB
210 Dhrystone MIPS
MIPS I, II, III, MIPS16
Single-cycle, 32-bit
2.5 V (core); 3.3 V (I/O)
Subset of ISA
128 MB DRAM
128 MB ROM
350 mW
224-pin FPBGA
10~70
o
C
0.25-micron UR2 process
V
R
4122
V
R
4120A
180 MHz
Instruction:
32 KB
Data:
16 KB
216
Dhrystone MIPS
MIPS I, II, III, MIPS16
Single-cycle, 32-bit
1.8 V
(core); 3.3 V (I/O)
PCI
, subset of ISA
128 MB DRAM
128 MB ROM
270 mW
224-pin FPBGA
10~70
o
C
0.18-micron
UC3 process
CPU Core
Max. Pipeline Clock
Cache Size
Performance
Instruction Set
MAC Instruction
Operating Voltage
Bus Supported
Memory Interface
Power Consumption
Package
Temperature Range
Process Technology
NEC Next-Generation Solution for H/PC
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