
F E AT U R E S
O R D E R I N G I N F O R M AT I O N
V
R
4120 CPU CORE
— MIPS I, II, III ISA-compliant
— MIPS16 ASE-compliant for compact code density
(40% denser code than MIPS32)
— Five-stage pipeline running up to 180 MHz
— Single-cycle 32-bit MAC instruction for DSP
operations
MEMORY MANAGEMENT UNIT
— 32-bit physical addressing range of 4 GB with 40-bit
virtual address space
— 32 double-entry TLBs supporting 1~256 KB page size
— Up 128-MB SDRAM/EDO/fast-page DRAM and
128-MB SROM/flash memory/mask ROM
CACHE MEMORY UNIT
— 32-KB direct-mapped instruction cache
— 16-KB direct-mapped data cache
BUS CONTROL UNIT
— 32-bit and 16-bit addressing mode
— Dynamic bus sizing to support subset of ISA bus
— PCI bus support
SERIAL INTERFACE UNIT
( 1 6 5 5 0 - C o m p a t i b l e )
— RS-232C Compliant
— 1.5-Mbps data transfers
— Separate serial debugging port
PCI BUS INTERFACE UNIT
— Supports 32-bit 33 MHz PCI bus
OTHER
—
Power management unit
with four power-saving
modes: full speed, standby, suspend, and hibernate
—
Clock generator unit
with built-in PLL for frequency
multiplication
—
Real-time clock
with four built-in timers
—
Interrupt control unit
that supports both internal
and external interrupts
—
DMA address unit and DMA control unit
that
controls three different types of DMA
—
General-purpose I/O unit
that controls 31
general-purpose I/O pins
—
Fast infrared unit
: 0.5 to 4 Mbps IrDA 1.1 standard
communication
SPECIFICATIONS
— 180 MHz maximum frequency
— 1.8 V (CPU Core) and 3.3 V (I/O) operation
— 270 mW at 180 MHz typical power consumption (target)
— 224-pin FPBGA package (16 x 16 x 1.3 mm)
— 0.18-micron CMOS Process Technology
PART NUMBER
μPD30122F1-150-GA1
μPD30122F1-180-GA1
PACKAGE
224-pin FPBGA
224-pin FPBGA
MAXIMUM OPERATING FREQUENCY
150 MHz
180 MHz