- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373842 > ZXFV4583N16TC (ZETEX PLC) SYNC SEPARATOR WITH VARIABLE FILTER PDF資料下載
參數(shù)資料
| 型號(hào)： | ZXFV4583N16TC |
| 廠商： | ZETEX PLC |
| 元件分類： | 信號(hào)分離 |
| 英文描述： | SYNC SEPARATOR WITH VARIABLE FILTER |
| 中文描述： | SYNC SEPARATOR IC, PDSO16 |
| 封裝： | MS-012AC, SO-16 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 212K |
| 代理商： | ZXFV4583N16TC |
DETAILED DESCRIPTION
Introduction
This deviceincludes allthefunctions requiredtoseparate
outthecriticaltiming pointsofmosttypesofvideosignal.
A sample-and-hold process is used to establish
accurately the 50% point of the sync pulse. The input is
also filtered to avoid the effect of the color carrier. The
filter is coupled externally. The following paragraphs
give a simplified description of the signal processing.
Color carrier filter
This low-pass filter provides adjustable attenuation of
the color carrier with low distortion of the remaining
sync pulses so as to ensure accurate timing of the
extracted logic outputs. The control is via an external
resistor R
FILT
connected from pin 1 to ground.
R
FILT
=22k
gives corner frequency of
～
1.3MHz
corresponding
to
~12dB
3.58MHz.(Corner freq. Proportional to 1/R
FILT
,
minimum value 18k ). A graph shows how the
bandwidth varies with the resistor value.
attenuation
@
Clamping circuits
Clamping circuits are use to limit the signal swing
excursion after AC coupling at both the input to the
filter, FILTIN and the timing extractor input, FVIDIN. In
each case, the sync tip level is maintained at a value of
nominally 1.35V.
Sync timing extraction circuits
The waveforms are depicted in Timing Diagrams,
Figure 1
for PAL (625 lines) and
Figure 2
for NTSC (525
lines).
Sample-and-hold circuits are used to obtain
time-delayed voltage values of the sync tip and the
back porch.
The sample gates are controlled by a
comparator sensing the video input relative to a
threshold at a fixed offset above the sync tip clamp
level.
The sampled voltages are combined in a
potential divider to derive the mean voltage (50%
amplitude), which is used as the sync pulse threshold.
A second comparator then provides
CSYNC
, the logic
version of the composite sync signal. This is delayed
slightly as shown in
Figure 3
.
comprises that of the input filter and also the smaller
delay of the comparator and logic. The timing of the
sample hold and other time parameters are all
controlled together in unison by the external resistor
R
SET
. A 1% resistor tolerance is recommended. The
sync tip voltage level from the sample-and-hold is
buffered and provided as an analog output,
VLEV.
The time delay
The vertical sync output
VSYNC
is derived from the
Field pulse group. Where there are short equalization
pulses in the standard systems, these short pulses are
ignored.
Essentially, a pulse width discriminator
circuit senses the first of the Field pulses, as they are
wider than those of the rest of the sequence.
trailing edge of the first negative-going Frame Pulse
(i.e. the rising edge of the first “serration” pulse)
triggers the VSYNC output. In systems with a frame
interval with no serration pulses, a vertical sync output
is provided after a default delay as in
Figure 4
. Also
provided is an
ODDFLD
logic output, which is high
during an odd-numbered field and low during an even
one.
The
The horizontal sync
HSYNC
is a monostable output
derived from the leading (falling) edge of the
composite sync. The pulse width is about 5 μs. Also,
during the Field blanking sequence, the additional
half-line pulses are removed by a timing circuit with a
pulse interval discrimination function controlled by
R
SET
. R
SET
is normally set to 681k
NTSC timings. Consequently the scan rate is inversely
proportional to R
SET
.
The Back Porch monostable output
BKPCH
is initiated
from thetrailing edgeofthecompositesync. Thepulse
is active low and the width is set according to R
SET
.
for standard PAL or
Loss-of-Signal detector
Loss of signal is indicated by a logic high level at the
output
NOSIG
. The decision threshold is set by an
external resistor R
NOSIG
connected from pin 2 to
ground. R
NOSIG
=100k
gives a shut off threshold of
～
250mV of sync amplitude at FVIDIN or ~130mV on
FILTIN (Threshold proportional to R
NOSIG
, minimum
value 82k ) The table of connections above gives the
equation used to determine a suitable resistorvalue. A
waiting time of nominally 600 μs occurs before the loss
of signal is flagged.
ZXFV4583
S E M IC O N D U C T O R S
ISSUE 3 - NOVEMBER 2003
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZXLD1601 | ADJUSTABLE DC - DC BOOST CONVERTER WITH INTERNAL SWITCH IN SC70 |
| ZXLD1615 | CHOPPER STABILIZED SWITCH W/TIN PLATING |
| ZXLD1615ET5 | SEE A3240ELT-T |
| ZXM61N03F | 30V N-CHANNEL ENHANCEMENT MODE MOSFET |
| ZXM61N03FTA | 30V N-CHANNEL ENHANCEMENT MODE MOSFET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZXFVX | 制造商:ZETEX 制造商全稱:ZETEX 功能描述:Quad, single, triple and dual video amplifiers |
| ZXGD3001E6 | 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:9A(peak) Gate driver in SOT23-6 |
| ZXGD3001E6TA | 功能描述:功率驅(qū)動(dòng)器IC 9A Gate Driver Mosfet RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| ZXGD3001E6TA-CUT TAPE | 制造商:DIODES 功能描述:ZXGD3001E6TA Single Channel 9 A High Side MosFet Driver - SOT-23-6 |
| ZXGD3002E6 | 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:9A(peak) Gate driver in SOT23-6 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。