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參數(shù)資料
| 型號(hào)： | ZXFV4583N16TC |
| 廠商： | ZETEX PLC |
| 元件分類(lèi)： | 信號(hào)分離 |
| 英文描述： | SYNC SEPARATOR WITH VARIABLE FILTER |
| 中文描述： | SYNC SEPARATOR IC, PDSO16 |
| 封裝： | MS-012AC, SO-16 |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大小： | 212K |
| 代理商： | ZXFV4583N16TC |
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ZXFV4583
S E M IC O N D U C T O R S
ISSUE 3 - NOVEMBER 2003
4
PIN No.
PIN NAME
TYPE
FUNCTION
1
R
FILT
Resistor
control
Controls the input color carrier filter characteristic. An external
resistor R
FILT
connected from this pin to 0V sets the bandwidth.
Smaller R
gives increased bandwidth. See the detailed operating
description below.
2
R
NOS IG
Resistor
control
Controls the no-signal detector level. An external resistor R
connected from this pin to 0V sets the threshold voltage level,
according to the equation
V
PMIN
= 0.75 R
NOS IG
/ R
S ET
where V
PMIN
is the minimum detected sync pulse amplitude at pin 4
and R
S ET
Composite sync logic output. Includes all sync pulses derived from
the input video.
3
CSYNC
Logic out
4
FILTIN
Analog in
Input to color carrier filter. This is the main analog (unfiltered)
composite video input used when color carrier filtering is required. A
voltage clamp circuit and adaptive current source are also included
at this node. See the detailed operating description. When the filter
is not used, this pin must be left open circuit.
5
VSYNC
Logic out
Vertical sync output. This is an active low pulse commencing on the
first vertical sync pulse trailing (rising) edge and ending near the
second next equalizing pulse. See timing diagram.
6
OVD
Ground
Provides ground return path for internal logic output buffer circuits.
Normally connected externally to a common PCB ground plane.
7
FILTOUT
Analog outis nominally 2. This output is normally capacitor-coupled to pin 8.
8
FVIDIN
Analog in
Input for filtered analog video signal input. This is the direct input
to the sample/hold and sync slicing comparator providing the logic
timing edges. This input is normally coupled via an external
capacitor from FILTOUT, pin 7. It may be used as the signal input
where the color carrier filter is not required. Includes a clamp
similar that of pin 4.
9
VLEV
Analog out(negative) peak sync pulse amplitude if the filter is used.
10
NOSIG
Logic out
Logic output, which goes high after a time-out delay when no signal
is present. The threshold level is controlled at pin 2.
11
BKPCH
Logic out
Burst or Back Porch logic output, an active low monostable pulse
triggered from rising composite sync pulse edges. The width is set
by R
to overlap most of the steady part of the back porch,
assuming the color carrier burst has been attenuated sufficiently by
filtering. This pulse is then suitable for controlling an external black
level clamping circuit. See the timing diagram.
12
R
S ET
Resistor
control
Controls the timing interval of the sample/hold circuit and the
monostable interval for the sync outputs according to the
application. An external resistor, R
connected from this pin to 0V
establishes the timing parameter, to which these times are scaled
together. See the detailed operating description.
13
ODDFLD
Logic out
Odd field logic output. High during an odd numbered field, low
during even. This output is timed with the start of the VSYNC pulse.
14
V+
Power in
Power supply input, +5V.
15
HSYNC
Logic out
Horizontal sync logic output. Monostable output derived from
CSYNC falling edges, it achieves a steady stream of 5μs pulses. The
half line events during the field blanking interval are eliminated. See
timing diagram.
CONNECTIONS
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