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參數(shù)資料
| 型號(hào)： | ZSP400 |
| 廠商： | LSI Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | A Synthesizable High-Performance 16-Bit Fixed Point Digital Signal Processor(DSP)(合成的、高性能16位定點(diǎn)數(shù)字信號(hào)處理器) |
| 中文描述： | 可合成高性能16位定點(diǎn)數(shù)字信號(hào)處理器（DSP）（合成的，高性能16位定點(diǎn)數(shù)字信號(hào)處理器） |
| 文件頁(yè)數(shù)： | 2/2頁(yè) |
| 文件大?。?/td> | 83K |
| 代理商： | ZSP400 |
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ZSP400 Digital Signal Processor Core
LSI Logic logo design, CoreWare and G12 are registered
trademarks of LSI Logic Corporation. All other brand and
product names may be trademarks of their respective companies.
LSI Logic Corporation reserves the right to make changes to
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lectual property rights of LSI Logic or of third parties.
Copyright 2000 by LSI Logic Corporation.
All rights reserved.
Order No. R20014
1001.5M – Printed in USA
ISO 9000 Certified
The ZSP400 can communicate off chip, while utilizing ROM for boot functions
or preset DSP algorithms and tables. Several boot routines can be provided,
including internal self-test, emulation code and JTAG port as well as boot-loader
routines. The peripheral interface provides glueless interfaces to industry-standard
32-bit synchronous burst SRAM and 16-bit asynchronous SRAMs and ROM
devices. The ZSP400 has integrated dual 16-bit on-board timers for real-time
interrupt generation and an In-Circuit-Emulation (ICE) debug capability. The
ZSP400 incorporates support of idle and sleep operating modes to reduce operating
power dissipation. Features in the ZSP400 include loop registers (4), register
shadowing and reverse carry addressing to enhance the performance of Fast
Fourier Transform (FFT) algorithm execution.
Figure 2: Integrating the ZSP400 with Customer Defined Memory and Peripherals
The ZSP Processor family is fully supported with a complete set of software
development tools, available for Windows 95/98/NT and Solaris 2 platforms.
The ZSP Architecture enables the C compiler to produce code unrivaled in code
density and execution speed by any DSP in its class, offering fast time to market
with minimal compromise on performance and cost. An integrated debug
environment is available for PC platforms, including a JTAG control port.
Up to 1M
Up to 1M
DMA
Periph
Periph
Ext. Memory
EMU
Customer-
Defined
Peripherals
Customer-
Defined
Memory
64b
32b
64b
Ext. Bus
ZSP400 Core
32b
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