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參數(shù)資料
| 型號： | ZSP400 |
| 廠商： | LSI Corporation |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | A Synthesizable High-Performance 16-Bit Fixed Point Digital Signal Processor(DSP)(合成的、高性能16位定點數(shù)字信號處理器) |
| 中文描述： | 可合成高性能16位定點數(shù)字信號處理器（DSP）（合成的，高性能16位定點數(shù)字信號處理器） |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 83K |
| 代理商： | ZSP400 |
DSP Core with Integrated Debug and Timer Capabilities
Overview
The ZSP400 is a synthesizable high-performance 16-bit fixed point Digital Signal
Processor (DSP) based upon the ZSP Architecture. The ZSP400 synthesizable
core is designed for utilization in customer design flow environments. The ZSP400
provides an optimized superscalar DSP processor that can support both control
and DSP algorithm functions efficiently with a peak of 800 MIPS operations.
The ZSP400 Core has been characterized as a 200 MHz processor core that can
issue and execute four instructions simultaneously while providing 400 million
multiply-accumulate operations per second. The ZSP400 Core can be embedded
with ARM, MIPS or other host processors on a single silicon device and
complemented with memory, Ethernet, WAN, telecom, memory and mixed signal
cores to provide complete system-on-a-chip functionality with the highest levels
of integration available in the industry today.
Figure 1: ZSP400 Core Block Diagram
Description
Existing customers of LSI Logic’s LSl401Z/402Z standard DSP product offerings
can utilize the ZSP400. The ZSP allows designers to utilize off-the-shelf DSP
processor solutions for their prototyping and low, volume product requirements
while incorporating a ZSP400 Core for integrated solutions. The on-chip memory
can be expanded up to the 1M word memory addressing of the ZSP400 Core.
ZSP400 Digital Signal Processor Core
Features
4 issue superscalar16-bit architecture
Dual multiplier accumulators
Dual ALUs
Orthogonal instruction set
Single-cycle execution of all instructions
Synthesizable RTL
5 nsec cycle time at 1.8 V (±5%) for
0.18 micron technology
Fully static design
Idle and sleep modes for low power
Single cycle add-compare-select
(ACS – Viterbi)
JTAG interface port
Complete software tool chain
-
Optimizing C compiler
-
Optimizing assembler
-
Linker/loader
-
Debugger
-
Evaluation board
Benefits
High performance without VLIW
programming difficulties
Using C compiler - good code size/
performance
Latest-generation technology in industry
200 MHz operation in production
Simple to integrate in SOC
Suitable for mobile/low-power applications
Suitable for communications ECC
algorithms
Data I/O in background does not limit
performance
Testability and debugging capabilities
Ability to bring applications to market
quickly
Instruction Unit
Pipeline
Control
Unit
Data Unit
64b
32b
64b
64b
64b
Interrupt Control
Register File
24x16b
ALU 1
ALU 2
MAC 2
MAC 1
ZSP400 Core
Debug
Unit
Bus I/F
Unit
D-Cache
12x64b
I-Cache
8x64b
32b
To peripherals and I/O
To
memory
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