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參數(shù)資料
| 型號： | ZR38650TQC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PROGRAMMABLE DIGITAL AUDIO PROCESSOR |
| 中文描述： | 可編程數(shù)字音頻處理器 |
| 文件頁數(shù)： | 37/66頁 |
| 文件大小： | 441K |
| 代理商： | ZR38650TQC |
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37
ZR38650
General Purpose Ports
Six single-bit general purpose ports may be individually selected
as an input or output in the GPIOC auxiliary register. If config-
ured as an input, its sampled state may be read in the GPIO
general register, or if an output, its state may be set by writing to
the GPIO register.
System Interface
The system interface consists of all external signal functions
other than Input/Output Ports plus the general and auxiliary reg-
isters which are associated with functional units and I/O
operation.
General Registers
In addition to the primary data flow and control flow of instruc-
tions between functional units on the two data buses, there is the
secondary control flow between the general and auxiliary regis-
ters for initialization and maintenance of operation. The following
general registers are all directly addressable on the Data Bus for
register-to-register, memory-to-register or register-to-memory
parallel transfers.
Some of the more important General Registers are described
next in detail.
Table 20: ADC and DAC Serial Ports Function Summary
Function
A Group
B Group
Grouping: AB = 0
3 Inputs (A, E, F)
4 Outputs (B, C, D, G)
Grouping: AB = 1
2 Inputs (A, E)
1 Input (F), 4 Outputs (B, C, D, G)
Word size
16, 18, 20, 24 bits
16, 18, 20, 24 bits
Frame size (bits/frame)
16, 24, 32, 64, 128, 192, 193, 256
16, 24, 32, 64, 128, 192, 193, 256
Synchronization
Word or Frame
Word or Frame
Source and slave clocking modes
Yes
Yes
Latching on rising or falling edge of clock
Yes
Yes (when port F belongs to Port group B)
Transmitting data on rising or falling edge of clock
Yes
Yes
External master clock input
No
Yes
Internal master clock output
Yes
Yes
Internal clock scaler
I
2
S format
12-bit Counter
12-bit Counter
Yes
Yes
TDM format
Yes
Yes
Left/Right justified formats
Yes
Yes
Table 21: The General Registers
Name
D0-7
A0-1
M0-7
I0-7
D0L
D0M
D0H
SRG_SPF
D1L
D1M
D1H
Bits
48
20
20
20
20
20
8
20
20
20
8
Description
Data Registers 0-7
Address Registers 0-7
Modulus Registers 0-7
Index Registers 0-7
Data Register 0 Low
Data Register 0 Middle
Data Register 0 High
S/PDIF Transmitter Data Register
Data Register 1 Low
Data Register 1 Middle
Data Register 1 High
RC
LC
LS
LE
20
20
20
20
20
20
20
20
20
20
20
20
20
20
12
2
1
20
20
6
2
Repeat Count Register
Loop Count Register. Stack of four.
Loop Start Register. Stack of four.
Loop End Register. Stack of four.
Status Register
Mode Register
Program Counter
Stack Pointer
Z Register for JSR and JSRQ
Serial Port A Data Register
Serial Port B Data Register
Serial Port C Data Register
Serial Port D Data Register
Pack Register
Data Bus Extension Register
Data Shifter
Interrupt Enable
Serial Port E Data Register
Serial Port F Data Register
General Purpose I/O Data Register
External Memory Wait-states
STATUS
MODE
PC
SP
Z
SRA
SRB
SRC
SRD
PACKREG
DBX
DS
IE
SRE
SRF
GPIO
WAIT
Table 21: The General Registers (Continued)
Name
Bits
Description
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