參數(shù)資料
型號(hào)： ZR36067PQC
廠商： Electronic Theatre Controls, Inc.
英文描述： AV PCI CONTROLLER
中文描述： 影音PCI控制器
文件頁數(shù)： 32/48頁
文件大?。?/td> 580K
代理商： ZR36067PQC
32
AV PCI CONTROLLER
13.18 I
2
C-Bus Register
This register contains the control bits of the I
2
C Bus.
13.19 PostOffice Register
This register contains the status (byte 3), control (byte 2) and
data (byte 0) parameters for PostOffice transfers.
27
RW
all
JPEGRepIRQEn
- JPEG Report Interrupt
Request Enable. When enabled and IntPinEn
is set to ‘1’, an interrupt request will be gener-
ated on the PCI Bus INTA output pin after the
end of each JPEG field/frame process.
When JPEGRepIRQEn is cleared, JPE-
GRepIRQ continues to reflect the JPEG
process status.
‘1’ - interrupt request enabled,
‘0’ - disabled (default value).
26:25
R
Reserved. Returns zero.
24
RW
all
IntPinEn
- INTA Pin Enable. When cleared,
none of the events that may cause an inter-
rupt request on the PCI Bus INTA pin is
enabled. Nevertheless the interrupt status
register continues to reflect all interrupt input
pins and internal interrupt requests.
‘1’ - every interrupt request is passed onto the
PCI Bus,
‘0’ - INTA disabled (default value).
23:0
R
Reserved. Returns zero.
Address Offset: 0x044
Bit
Type
Mod
Description
31:2
R
Unused. Returns zero.
SDA
- I
2
C SDA Line. When the host writes ‘0’
to this bit, the SDA output signal goes low.
When the host writes ‘1’, SDA goes into tri-
state. When the host reads this bit it reflects
the current level on the SDA pin.
Default value is ‘1’.
SCL
- I
2
C SCL Line. When the host writes ‘0’
to this bit, the SCL output signal goes low.
When the host writes ‘1’, SCL goes into tri-
state. When the host reads this bit it reflects
the current level on the SCL pin.
Default value is ‘1’.
1
RW
all
0
RW
all
Address Offset: 0x040 (Continued)
Bit
Type
Mod
Description
Address Offset: 0x200 - 0x2FF
Bit
Type
Mod
Description
31:26
R
Reserved. Returns zero.
25
R
all
POPen
- PostOffice Request Pending flag.
This bit is set internally to ‘1’ when the host
writes to the PostOffice data byte.
It is cleared when a PostOffice cycle is com-
pleted or a PostOffice time-out occurred.
In case of concurrent accesses to this bit, the
result is ‘0’.
‘1’ - PostOffice request is pending.
‘0’ - PostOffice request is not pending (default
value).
24
RC
all
POTime
- PostOffice Time-out flag. This bit is
set to ‘1’ by the GuestBus master if a PostOf-
fice cycle on the GuestBus lasts more than 64
PCI clocks. This might happen when the
accessed guest holds GWS low for too long.
It is cleared (‘0’) by the host writing a ‘1’.
In case of concurrent accesses to this bit, it
remains ‘1’.
‘1’ - PostOffice cycle has timed out.
‘0’ - no time-out occurred (default value).
23
RW
all
PODir
- PostOffice Direction flag. This bit
defines the direction of the PostOffice opera-
tion:
‘0’ - Read (host reads guest).
‘1’ - Write (host writes to guest).
Default after reset is ‘1’.
22: 20
RW
all
POGuestID
- PostOffice Guest Identification.
These three bits select the guest to be
accessed. They determine which of the GCS
pins will be asserted in the requested PostOf-
fice cycle. Up to eight guests can be
identified.
Default after reset is 000b.
19
R
Reserved. Returns zero.
18:16
RW
all
POGuestReg
- PostOffice Guest Register.
Register indication of accessed guest. Within
each guest up to eight registers can be
addressed. The POGuestReg bits determine
the register address that will be presented on
the GADR2:0 lines in the requested PostOf-
fice cycle.
Default after reset is 000b.
15:8
R
Reserved. Returns zero.
POData
-
PostOffice Data. An eight-bit
register containing the data being transferred
during PostOffice reads and writes.
Default after reset is 00000000b.
7:0
R, W
all
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