- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373821 > ZR36050 (Zoran Corporation) JPEG Image Compression Processor(JPEG 圖象壓縮處理器) PDF資料下載
參數(shù)資料
| 型號(hào)： | ZR36050 |
| 廠商： | Zoran Corporation |
| 英文描述： | JPEG Image Compression Processor(JPEG 圖象壓縮處理器) |
| 中文描述： | JPEG圖像壓縮處理器（JPEG格式圖象壓縮處理器） |
| 文件頁數(shù)： | 5/52頁 |
| 文件大?。?/td> | 262K |
| 代理商： | ZR36050 |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
ZR36050
5
ADVANCE INFORMATION
DSYNC
I
O
Data Synchronization. This active- low signal is an input in encoding and output in decoding modes.
In the encoding modes, DSYNC marks the start of an 8x8 image data block and should appear as an
input one CLK_IN before the first image data of a block. In the decoding modes, DSYNC is output
one CLK_IN before the first image data sample of a block. The width of DSYNC is one CLK_IN cycle.
In the Fast Preview mode, and the Lossless encoding and decoding modes, this signal precedes
each image data sample.
EOS
I
O
End Of Scan. This active-low signal is an input in encoding modes. EOS indicates the last image data
sample of each scan entering the ZR36050. In encoding modes, EOS must be input regardless of the
STOP signal.
EOS is an output signal in the decoding mode. It is generated together with the last image data
sample of each scan leaving the ZR36050. In this case, DSYNC will not be issued.
In the Fast Preview and Lossless decoding modes, EOS is output within 64 CLK_IN cycles after the
last sample of a scan. It is merely used in as an indication of the completion of the current process
without having any timing significance.
In decoding mode, EOS is output regardless of the STOP signal.
The width of EOS is one CLK_IN cycle.
COEF(10-0)
O
O
Coefficient Bus. This 11-bit output bus is used to transfer DCT coefficients out of the device in the
encoding and decoding modes. The DCT coefficients are output in column-major order. This bus is
not used in the Fast Preview and Lossless encoding and decoding modes.
CSYNC
O
O
Coefficient Synchronization. This active-low signal indicates the beginning of an 8x8 DCT coefficient
block.
In the encoding and decoding modes, this signal is generated by the ZR36050. It is asserted one
CLK_IN cycle before the first coefficient of a block is placed on the COEF bus by the ZR36050. The
width of CSYNC is one CLK_IN cycle.
CSYNC is not used in the Fast Preview and Lossless encoding and decoding modes.
CODE(7-0)
O
I
Code. In Master mode Compressed Data Transfer, this 8-bit bidirectional bus is used to read the com-
pressed data from or write to the Compressed Data Memory.
In the 16-bit Slave and DMA modes, this bus is used as an extension of the DATA bus.
COE
-
O
Compressed Data Memory Read. This active-low output signal acts as a read pulse from the
ZR36050 to the Compressed Data Memory. COE goes active 0.5 CLK_IN cycles after the start of a
read cycle and remains active until the end of the read cycle. The CODE bus is latched on the rising
edge of COE.
CWE
O
-
Compressed Data Memory Write. This active-low output signal acts as a write pulse from the
ZR36050 to the Compressed Data Memory. CWE goes active 0.5 CLK_IN cycles after the start of a
write cycle and remains active until the end of the write cycle.
CCS
O
O
Compressed Data Memory Chip Select. This active-low output signal acts as a chip select signal from
the ZR36050 to the Compressed Data Memory. CCS goes active at the start of a read or write cycle
and remains active throughout the cycle. CCS remains active continuously in back to back read or
write cycles. The length of a read or write cycle can be from one to eight CLK_IN periods.
CAEN
O
O
Address Counter Enable. This active-low output signal can be used to advance an external Com-
pressed Data Memory address counter.
Table 1. Signal Description
1, 2
(Continued)
Signal
Type
3
Description
Encode
Decode
1. The DATA, CODE, PIXEL, and COEF buses have internal pull-downs that provide 50 microamps of pull-down current at 0.4 volts.
2. The control pins: DSYNC, EOS, STOP, END, CL, CSYNC, COE, CWE, CCS, CAEN, INT, DINT, DREQ and COMP, have internal pull-up
devices that provide 50 microamps at 2.4 volts. These pull-ups are turned on only when STDBY is active but RESET is inactive. When STDBY
is active together with RESET, the above control pins float.
3. I = Input, O = Output, B = Bidirectional, S = Supply.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR36060 | Integrated JPEG Codec(集成JPEG編解碼器) |
| ZR36060 | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| ZR36060PQC | Integrated JPEG CODEC |
| ZR36067 | AV PCI CONTROLLER |
| ZR36067PQC | AV PCI CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36050PQC-21 | 制造商:ZORAN 功能描述: |
| ZR36050PQC27 | 制造商:ZORAN 功能描述:* |
| ZR36050PQC-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:JPEG IMAGE COMPRESSION PROCESSOR |
| ZR36050PQC-29.5 | 制造商:Zoran Corp 功能描述:Peripheral IC |
| ZR36053TQC15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。