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參數(shù)資料
| 型號(hào)： | ZR36050 |
| 廠商： | Zoran Corporation |
| 英文描述： | JPEG Image Compression Processor(JPEG 圖象壓縮處理器) |
| 中文描述： | JPEG圖像壓縮處理器（JPEG格式圖象壓縮處理器） |
| 文件頁數(shù)： | 19/52頁 |
| 文件大小： | 262K |
| 代理商： | ZR36050 |
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ZR36050
19
ADVANCE INFORMATION
INTERFACES
Interrupt Acknowledgment Cycle
The Host Interface activates INT when one of the STATUS_0 or
STATUS_1 register bits (with the exception of the DATRDY bit)
becomes active, and the corresponding bit in INT_REQ_0 or
INT_REQ_1 is set. When the host reads the status register con-
taining the active bit, or gives the GO command, the status
register is cleared and the Host Interface deactivates INT.
Figure 10 shows activation of INT, and its deactivation in
response to a status read.
Slave Mode Compressed Data Transfer
In Slave mode, the host reads the compressed data from the
memory-mapped Compressed Data register in encoding, or
writes it into this register in decoding. Compressed data transfers
can be 8 or 16 bits wide, as specified by the BSWD bit in the
HARDWARE register. In a 16 bit transfer, the CODE bus acts as
an extension of the DATA bus. The lower numbered byte (the
byte that would have been transferred earlier in 8 bit transfers) is
read or written on the CODE or DATA bus, depending on the
BELE bit in the HARDWARE register. In 16-bit transfers, if the
last transfer of compressed data requires only one byte, the
ZR36050 appends a FF byte to complete the 16 bits in encoding,
and in decoding, the host can append an arbitrary byte.
Figure 9. Parameter Write by Host
ADDR
CS
WR
DATA (in)
SAMPLE
DATA
Figure 10. Interrupt Acknowledgment by Read
of the Status Register
ADDR
CS
RD
ADDRESS OF STATUS REGISTER
INT
In the diagrams illustrating operation of the interfaces, an arrow
linking signal transitions indicates the causal relationship of the
transitions. An arrow terminating on a circle designates the point
at which the indicated signal is sampled.
Host Interface
The Host Interface is used to access the Internal Memory
(Control Registers and JPEG Marker Segments) of the
ZR36050. It can also optionally be used to transfer the com-
pressed data to and from the ZR36050. There are 4 categories
of host interface bus cycle:
I
Internal Memory read and write by the host
I
Interrupt acknowledgment
I
Slave mode Compressed Data Transfer
I
DMA mode Compressed Data Transfer
Note that, although the Host Interface behaves as an asynchro-
nous interface, its control signals are internally synchronized to
CLK_IN, and CLK_IN must be toggling and enabled by CLKEN
in order for the Host Interface to operate.
Internal Memory Read and Write
Internal Memory read and write by the host is always 8 bits wide,
using the DATA, ADDR, CS, RD, and WR signal pins.
Figure 8 and Figure 9 show read and write cycles, respectively.
A bus cycle starts when the host drives CS low, and ends when
CS goes high. ADDR and CS must be stable throughout the
cycle and must overlap the RD or WR pulse. ADDR is sampled
with the falling edge of RD or WR.
In a read cycle, the Host Interface drives the DATA bus when CS
and RD are both active.
In a write cycle the Host Interface latches the data on the rising
edge of WR. Data must be valid before the trailing edge of WR;
it need not be valid before the leading edge. Note that the GO
command is a write of arbitrary data to address 0.
ADDR
CS
RD
DATA (out)
Figure 8. Parameter Read by Host
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36050PQC-21 | 制造商:ZORAN 功能描述: |
| ZR36050PQC27 | 制造商:ZORAN 功能描述:* |
| ZR36050PQC-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:JPEG IMAGE COMPRESSION PROCESSOR |
| ZR36050PQC-29.5 | 制造商:Zoran Corp 功能描述:Peripheral IC |
| ZR36053TQC15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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