參數(shù)資料
型號： ZPSD512B1-15U
英文描述： Field-Programmable Peripheral
中文描述： 現(xiàn)場可編程外圍
文件頁數(shù)： 85/153頁
文件大小： 1036K
代理商： ZPSD512B1-15U
PSD5XX Famly
82
Address
Ofset
Register Name
Address
Ofset
Register Name
+A8h
STATUS FLAGS
+A9h
GLOBAL COMMAND
+A7h
DLCY
+A4h
SOFTWARE LOAD/STORE
+A5h
FREEZE COMMAND
+A2h
CMD3
+A3h
CMD2
+A0h
CMD1
+A1h
CMD0
+9Eh
CNTR3
+9Fh
CNTR3
+9Ch
CNTR2
+9Dh
CNTR2
+9Ah
CNTR1
+9Bh
CNTR1
+98h
CNTR0
+99h
CNTR0
+96h
IMG3
+97h
IMG3
+94h
IMG2
+95h
IMG2
+92h
IMG1
+93h
IMG1
+90h
IMG0
+91h
IMG0
Table 23a. Ofset Address Map of Counter/Timer-Unit Registers
(For 16-Bit Motorola MCUs in 16-Bit Mode. If 8-Bit Mode is selected, use Table 23.)
Registers IMG0 through IMG3 are written to by the microcontroller to load the
Counter/Timers with required values in Waveform, Pulse and WatchDog mode only.
To retrieve the count or time in Event count or Time capture modes, Counter/Timers store
their values into IMG0 through IMG3.
Any access to the Image Registers must conform to the Freeze/Freeze Acknowledge
protocol, described later in the Freeze Command paragraph.
Counter/Timer
Registers
(Cont.)
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