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| 型號(hào)： | ZPSD512B1-15U |
| 英文描述： | Field-Programmable Peripheral |
| 中文描述： | 現(xiàn)場(chǎng)可編程外圍 |
| 文件頁(yè)數(shù)： | 45/153頁(yè) |
| 文件大?。?/td> | 1036K |
| 代理商： | ZPSD512B1-15U |
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PSD5XX Famly
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9.3.10 Port Registers
There are two sets of registers per I/O port: the Port Configuration Registers (PCR) which
consist of four 8-bit registers; and the Port Data Registers (PDR) which include three 8-bit
registers. The PCR is used for setting up the port configuration, while the PDR enables the
microcontroller to write or read port data or status bits. Tables 12 and 13 show the names
and the registers and the ports to which they belong.
All the registers in the PCR and PDR are 8-bits wide and each bit is associated with a pin in
the I/O port. In Table 14, the LSB of the Data In Register of Port A is connected to pin PA0,
and the MSB is connected to PA7. This pin configuration also applies to other registers and
ports. For example, in the Direction Register of Port A, writing a hex value of 07 to the
register configures pins PA0 – PA2 as output pins, while PA3 – PA7 remain as input pins.
Registers can be accessed by the microcontroller during normal read/write bus cycles.
The I/O address offset of the registers are listed in the System Configuration section.
I/OPorts
(Cont.)
Register Name
Port
Write/Read
Control Register
A,B,C,D,E
Write/Read
Direction Register
A,B,C,D,E
Write/Read
Open Drain Register
C,D
Write/Read
Special Function Register
A,B,E
Write/Read
PLD – I/O Register
A,B,E
Read
Table 12. Port Configuration Registers (PCR)
Register Name
Port
Read/Write
Data In Register
A,B,C,D,E
Read
Data Out Register
A,B,C,D,E
Write/Read
Macrocell Out Register
A,B,E
Read
Table 13. Port Data Registers (PDR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7 Pin
PA6 Pin
PA5 Pin
PA4 Pin
PA3 Pin
PA2 Pin
PA1 Pin
PA0 Pin
Table 14.
Data In Register – Port A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA7 Pin
PA6 Pin
PA5 Pin
PA4 Pin
PA3 Pin
PA2 Pin
PA1 Pin
PA0 Pin
= 0
= 0
= 0
= 0
= 0
= 1
= 1
= 1
Drection Register – Port A
(Example: Pins PA0 – PA2 as Output, PA3 – PA7 as Input)
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