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參數(shù)資料
| 型號(hào)： | ZPSD512B1-15LI |
| 英文描述： | Schottky Barrier Diodes |
| 中文描述： | 肖特基勢(shì)壘二極管 |
| 文件頁(yè)數(shù)： | 4/153頁(yè) |
| 文件大?。?/td> | 1036K |
| 代理商： | ZPSD512B1-15LI |
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1
1.0
Introduction
Programmable Peripheral
PSD5XX Famly
Field-Programmable Microcontroller Peripherals
The PSD5XX family is a microcontroller peripheral that integrates high-performance and
user-configurable blocks of EPROM, programmable logic, and SRAM into one part. The
PSD5XX is also loaded with a variety of features, such as Counter/Timers, Interrupt
controller, power management, and page logic. The PSD5XX products also provide a
powerful microcontroller interface that eliminates the need for external “glue logic”. The no
“glue logic” concept provides a user-programmable interface to a variety of 8- and 16-bit
(multiplexed or non-multiplexed) microcontrollers that is easy to use. The part’s integration,
small form factor, low power consumption, and ease of use make it the ideal part for
interfacing to virtually any microcontroller.
The PSD5XX provides three Zero-power PLDs (ZPLDs): a Decode PLD (DPLD), a
General-purpose PLD (PLD), and a Peripheral PLD (PPLD). The ZPLDs have a total of 61
inputs, 140 product terms, 30 macrocells, and 24 I/O connections. A configuration bit
(Turbo) can be set by the MCU, and will automatically place the ZPLDs into standby if
no inputs are changing. The ZPLDs are designed to consume minimum power using Zero
Power CMOS technology that uses low standby current. Unused product terms are
automatically disabled, also reducing power, regardless of the Turbo bit setting.
The main function of the DPLD is to perform address decoding for the internal I/O ports,
EPROM, and SRAM. The address decoding can be based on up to 24 bits of address
inputs, control signals (RD, WR, PSEN, etc.), and internal page logic. The DPLD supports
separate program and data spaces (for 8031 compatible MCUs).
The General-purpose PLD (GPLD) can be used to implement various logic defined by the
user, such as:
State machines
Loadable counters and shift registers
Inter-processor mailbox
External control logic (chip selects, output enables, etc.).
The GPLD has access to up to 61 inputs, 118 product terms, 24 macrocells, and 24 I/O
pins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZPSD512B1-15LM | Field-Programmable Peripheral |
| ZPSD512B1-15U | Field-Programmable Peripheral |
| ZPSD512B1-15UI | Field-Programmable Peripheral |
| ZPSD512B1-20J | Field-Programmable Peripheral |
| ZPSD512B1-20JI | Field-Programmable Peripheral |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZPSD512B1-C-90UI | 制造商:WSI 功能描述: |
| ZPSD513B1-C-15L | 制造商:WSI 功能描述: |
| ZPSD602E1-15L | 制造商:WSI 功能描述: |
| ZPSD611E1-15J | 制造商:WSI 功能描述: |
| ZPSD611E1-15JI | 制造商:WSI 功能描述: |
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