參數(shù)資料
型號: ZPSD511B1V
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗,16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設備(可編程邏輯,零功耗,16K的位的SRAM,40余個可編程輸入/輸出,通用PLD的有61個輸入)
文件頁數(shù): 105/142頁
文件大?。?/td> 786K
代理商: ZPSD511B1V
ZPSD5XX Famly
7-105
System
Configuration
(Cont.)
Register Name
Address
Ofset
Register Name
Address
Ofset
PAGE REGISTER
E0
INTR. READ CLEAR
D4
INTR. MASK
D3
INTR. EDGE/LEVEL
D2
INTR. REQUEST
LATCH
D1
INTR. PRIORITY
STATUS
D0
VM
C0
PMMR1
B1
PMMR0
B0
STATUS FLAGS
A9
GLOBAL COMMAND
A8
DLCY
A6
SOFTWARE
LOAD/STORE
A5
FREEZE COMMAND
A4
CMD3
A3
CMD2
A2
CMD1
A1
CMD0
A0
CNTR3
9F
CNTR3
9E
CNTR2
9D
CNTR2
9C
CNTR1
9B
CNTR1
9A
CNTR0
99
CNTR0
98
IMG3
97
IMG3
96
IMG2
95
IMG2
94
IMG1
93
IMG1
92
IMG0
91
IMG0
90
Table 31. Oher Register Address Ofset
The following table is the address map offset of registers for the I/O ports.
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