參數(shù)資料
型號： ZPSD503B1-90U
英文描述： Field-Programmable Peripheral
中文描述： 現(xiàn)場可編程外圍
文件頁數(shù)： 74/153頁
文件大?。?/td> 1036K
代理商： ZPSD503B1-90U
PSD5XX Famly
71
9.6.1.3 Pulse Mode
In Pulse mode, the Counter/Timer is capable of generating a one shot pulse. The Pulse
width of the generated pulse is defined by the value loaded into the associated Image
register of the timer. If the Counter/Timer register is directly loaded by the MCU, it gets
overwritten by the associated Image register contents as soon as the Counter/Timer
is active. Each CTU is capable of pulse mode. As soon as the Timer is active,
i.e. decrementing or incrementing, a pulse is output until the Timer underflows or overflows.
The pulse waveform is illustrated in Figure 36. The active level of this pulse is defined
again by a command register bit. As can be seen in Figure 37, the pulse is triggered by any
of the following events:
J
Transition on the input pin (Port E) (If enabled by software).
J
PPLD macrocell output pulses (If enabled by software).
J
Command register bit is written to by a Microcontroller (Software load).
As in the waveform mode, the polarity of the input pin is defined by a command register
bit and the Freeze/Freeze Acknowledge must be used whenever the image register is
modified.
The outputs of CTU0, CTU1, CTU2 and CTU3 are available at Port A and Port B. Refer to
Tables 25 and 26 for further details and configuration of these ports.
9.6.1.4 Event Counter Mode
In this mode, the Counter/Timer uses the CTU to count a number of events. An event is
defined as a signal-transition on the Counter’s input pin as defined by the input polarity
configuration bit in the Command Registers or a Low to High transition on the PPLD
Macrocell output. In this mode, the image register of the CTU is used to store the contents
of the Counter at the rising edge of the Load/Store signal. This is opposed to the previous
two modes in which the image register was used to load the Counter. Figure 38 shows the
configuration of the CTU for the event-Counter mode. Notice that the enable signal is edge
sensitive. Its source is either:
J
Pin Driven.
J
PPLD Macrocell Driven.
All Counter/Timer registers must be assigned values during initialization in the Event
Counter mode. During normal operation, the CTU increments or decrements its count
when an event occurs. The image register is then immediately updated with the current
count. The microcontroller can read the contents of the image register by first setting the
command-register Freeze bit in order to disable count updates of the image register during
its read operation. The microcontroller waits for a freeze acknowledge and then accesses
the image register in the usual fashion. The Freeze signal effectively guarantees stable
image register data during microcontroller read access, even though the CTU continues to
count events. During the Freeze Acknowledge active state, the counter continues counting.
Note that for an event to be counted the events must be separated by at least one timer
clock period plus two CLKIN clock periods.
Counter/Timer
Operation
(Cont.)
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