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| 型號(hào)： | ZPSD503B1-90U |
| 英文描述： | Field-Programmable Peripheral |
| 中文描述： | 現(xiàn)場(chǎng)可編程外圍 |
| 文件頁(yè)數(shù)： | 71/153頁(yè) |
| 文件大小： | 1036K |
| 代理商： | ZPSD503B1-90U |
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PSD5XX Famly
68
9.6.1.2 WaveformMode
In Waveform mode, the Counter/Timer is capable of producing various pulse-width
modulated (PWM) signals. The Waveform mode in the PSD5XX is realized using two CTUs
(COUNTER/TIMER UNITs) in the following combinations:
CTU0 & CTU1 or CTU2 & CTU3.
The outputs of CTU0 and CTU2 are available at Port A and Port B. Refer to Tables 25 and
26 for further details and configuration of these ports. CTU1 and CTU3 are internally
connected to CTU0 and CTU2. The Waveform mode is illustrated in Figure 34 which shows
a typical PWM waveform and the time slots in which two CTUs are active. The Waveform
period is the sum of the counts for CTU0 and CTU1 (see equation 1), while the duty cycle is
given by equation 2. The Duty cycle of a waveform can be changed by loading a new value
into the corresponding IMAGE register, and as soon as a Terminal Count is generated this
new value gets loaded into the CTU. Note that the end of a CTU time slot is indicated with
Terminal Count signal of the active CTU. The Terminal Count signals are used to signal the
transfer of active status between CTUs. The Terminal Count is true whenever the Counter
underflows while decrementing or when the Counter overflows while incrementing.
PERIOD of the waveform generated
= COUNT HIGH + COUNT LOW..(1)
DUTY Cycle of the Waveform Generated
=COUNT HIGH
COUNT HIGH + COUNT LOW......(2)
The timing of various pulses that create a Waveform signal in the above example is defined
by the Microcontroller via image register updates of the CTU0 and CTU1. The contents of
an image register are loaded or copied to the associated Counter under any of the following
conditions:
J
Terminal Count of CTU1 and/or CTU3 pulses to transfer active status to CTU0
and/or CTU2.
J
An input pin (port E) pulses (If enabled by software).
J
A PPLD macrocell output pulses (If enabled by software).
J
A command register bit is written to by the Microcontroller, i.e., a software
Load/Store (load).
A Waveform output is first initialized and then later modified by setting its two corresponding
software Load/Store bits after loading of the Image Registers. If the Counter/Timer register
is directly loaded by the MCU, it gets overwritten by the associated Image register contents
as soon as the Counter/Timer is active. The configuration of the CTU in the waveform mode
is schematically illustrated in Figure 35.
The output polarity during the CTU0 time slot is controlled by bit 3 in the Counter/Timer
command register. The output polarity during the CTU1 time slot is defined as the
complement of the CTU0 polarity. Similarly, the polarity of the input pin is controlled by bit 4
in the Counter/Timer command register. This description of the waveform mode of operation
applies to CTU2 and CTU3 also.
In order to change the image register values, use the Freeze/Freeze Acknowledge protocol
as described in the Freeze Command Register section.
Counter/Timer
Operation
(Cont.)
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