參數(shù)資料
型號: ZPSD502B1-12UI
英文描述: Field-Programmable Peripheral
中文描述: 現(xiàn)場可編程外圍
文件頁數(shù): 119/153頁
文件大?。?/td> 1036K
代理商: ZPSD502B1-12UI
PSD5XX Famly
116
-70
-90*
-15
EPROM_CMiser
ON
Symbol
Parameter
Conditions
Min Max Min Max Min Max
Unit
t
LVLX
t
AVLX
t
LXAX
ALE or AS Pulse Width
18
20
28
ns
Address Setup Time
(Note 1)
5
6
10
ns
Address Hold Time
(Note 1)
7
8
11
ns
t
AVWL
Address Valid to
Leading Edge of WR
(Notes 1 and 3)
18
20
30
ns
t
SLWL
CS Valid to Leading
Edge of WR
(Note 3)
22
25
35
ns
t
DVWH
t
WHDX
t
WLWH
WR Data Setup Time
(Note 3)
12
15
22
ns
WR Data Hold Time
(Note 3)
5
5
5
ns
WR Pulse Width
(Note 3)
18
20
28
ns
t
WHAX
Trailing Edge of WR to
Address Invalid
(Note 3)
0
0
0
ns
t
WHPV
Trailing Edge of WR to
Port Output Valid
(Note 3)
25
30
38
ns
In 16-Bit Data Bus
Mode (Note 2)
20
30
38
ns
Address Input Valid to
Address Output Delay
t
AVPV
In 8-Bit Data Bus
Mode (Note 2)
22
32
48
ns
Write Timng
(5 V ± 10%)
Microcontroller Interface – AC/DC Parameters
(5 V ± 10% Versions)
NOTES:
1.
Any input used to select an internal PSD5XX function.
In multiplexed mode latched address generated from ADIO delay to address output on any Port.
WR timing has the same timing as E, DS, LDS, UDS, WRL, WRH signals.
2.
3.
*
The -90 speed is available only on Industrial Temperature Range product.
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