參數(shù)資料
型號： ZPSD501B1V
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入）
文件頁數(shù)： 86/142頁
文件大?。?/td> 786K
代理商： ZPSD501B1V
ZPSD5XX Famly
7-86
Command Registers for Counter/Timers CMD0, CMD1, CMD2, CMD3 (Cont.)
Output Polarity Bit (3):
This bit is valid only in Waveform or Pulse mode and is
used to select the polarity of the Active output signal
of the Counter/Timer0. At RESET this bit initializes as 0
which means the Active output state is LOW. When this bit
is set to a
1: The Active output state is HIGH.
0: The Active output state is LOW.
Input Polarity Bit (4):
The state of this bit determines the polarity of the Active
input control signal to the Counter/Timer0 and is valid only
for input pin. At RESET this bit initializes as 0 which means
that the input Active is HIGH. When this bit is set to a
1: The input Active is LOW.
0: The input Active is HIGH.
Pin / PPLD Macrocell Bit (5):
This bit determines whether the Counter/Timer0 gets its
input command for Load/Store and Enable/Disable from
the ZPSD5XX PIN or from the PPLD macrocell output.
At RESET this bit initializes as 0 which means that the
input command is coming from the ZPSD5XX PPLD
macrocell. When this bit is set to a
1: The Counter/Timer0 input command is coming from
the PIN.
0: The Counter/Timer0 input command is coming
from the PPLD macrocell output.
Software Gating Bit for
Load/Store Commands (6):
This bit gates the Load/Store command activated by the
ZPSD5XX PIN or PPLD macrocell. At RESET this bit
initializes as 0 which means that the Load/Store command
activated by the PIN or macrocell is permitted through.
When this bit is set to
1: Load/Store operation activated by PIN or Macrocell is
NOT permitted through.
0: Load/Store operation activated by PIN or macrocell is
permitted through. To further decide between the PIN
and PPLD macrocell, use bit 5 (PIN/PPLD macrocell).
Enable/Disable Using PIN,
PPLD Macrocell or Software
command is activated by the ZPSD5XX Pin, PPLD
macrocell or by Software. At RESET this bit initializes as 0,
Bit (7):
which means that the Enable/Disable command is
activated by the PIN or PPLD macrocell. When this bit is
set to
1: Enable/Disable command by PIN or macrocell is
overridden by Software (only Bit 2 of this register will
enable or disable the counter).
0: Enable/Disable command is activated by PIN or
Macrocell output. To further decide between the PIN and
PPLD macrocell use bit 5 (PIN / PPLD macrocell bit).
This bit determines whether the Enable/Disable
Counter/Timer
Registers
(Cont.)
相關(guān)PDF資料
PDF描述
ZPSD503B1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
ZPSD503B1V Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
ZPSD511B1 Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
ZPSD511B1V Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入)
ZPSD602(V)E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
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