參數(shù)資料
型號： ZPSD4XX
廠商： 意法半導(dǎo)體
英文描述： Low Cost Field Programmable Microcontroller Peripherals
中文描述： 低成本現(xiàn)場可編程微控制器外圍設(shè)備
文件頁數(shù)： 94/123頁
文件大?。?/td> 657K
代理商： ZPSD4XX
PSD4XX Famly
91
-20
-25
EPROM_CMiser
ON
Symbol
t
LVLX
t
AVLX
t
LXAX
t
AVQV
t
SLQV
Parameter
Conditions
Min Max Min Max
Unit
ALE or AS Pulse Width
30
30
0
ns
Address Setup Time
(Note 3)
12
15
0
ns
Address Hold Time
(Note 3)
12
17
0
ns
Address Valid to Data Valid
(Note 3)
200
250
Add 20
ns
CS Valid to Data Valid
200
275
Add 20
ns
RD to Data Valid 8/16-Bit Bus
(Note 1)
50
80
0
ns
t
RLQV
RD to Data Valid 8-Bit Bus,
8031 Separate Mode
(Note 2)
57
90
0
ns
t
RHQX
t
RLRH
t
RHQZ
t
EHEL
t
THEH
t
ELTL
RD Data Hold Time
(Note 1)
0
0
0
ns
RD Pulse Width
(Note 1)
40
70
0
ns
RD to Data High-Z
(Note 1)
45
45
0
ns
E Pulse Width
40
70
0
ns
R/W Setup Time to Enable
20
15
0
ns
R/W Hold Time After Enable
0
0
0
ns
In 16-Bit Data Bus
Mode (Note 4)
Address Input Valid to
Address Output Delay
40
60
0
ns
t
AVPV
In 8-Bit Data Bus
Mode (Note 4)
50
60
0
ns
Read Timng
(3.0 V ± 10%)
Explanation of AC Symbols for Non ZPLD Timing.
Example:
t
AVLX
Time from Address Valid to ALE Invalid.
A
– Address
C
– Power Down
D
– Input Data
E
– E
H
– Logic Level High
I
– Interrupt
L
– Logic Level Low or ALE
N
– Reset
P
– Port Signal
Q
– Output Data
R
– WR, UDS, LDS, DS, IORD, PSEN
S
– Chip Select
T
– R/W
t
– Time
V
– Valid
X
– No Longer a Valid Logic Level
Z
– Float
13.11 Microcontroller Interface – AC/DC Parameters (ZPSD4XXV Versions)
(3.0 V ± 10%)
NOTES:
1. RD timing has the same timing as PSEN, DS, LDS, UDS signals.
2. RD and PSEN have the same timing for 8031 mode.
3. Any input used to select an internal PSD4XX function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
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