參數(shù)資料
型號(hào)： ZPSD312
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,4位頁寄存器,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，4位頁寄存器，19個(gè)可編程的I / O，通用PLD的有16個(gè)輸入）
文件頁數(shù)： 23/90頁
文件大小： 491K
代理商： ZPSD312
ZPSD3XX Famly
3-23
SRAM
EPROM
Memory Paging
(ZPSD3X2/3X3/
3X4R)
The zero power EPROM has 8 banks of memory. Each bank can be placed in any address
location by programming the PAD. Bank0–Bank7 is selected by PAD outputs ES0–ES7,
respectively.
The EPROM powers up only on address change and consumes power for the necessary
time to latch data on its outputs. It then powers down and remains in standby mode.
Each ZPSD3XX device (except SRAMless Versions) has 16K bits of zero power SRAM.
Depending on the configuration of the data bus, the SRAM organization can be 2K x 8
(8-bit data bus) or 1K x 16 (16-bit data bus). The SRAM is selected by the RS0 output of
the PAD.
The SRAM powers up only on address change and consumes power for the necessary
time to latch data on its outputs. It then powers down and remains in standby mode.
The page register consists of four flip-flops, which can be read from, or written to, through
the I/O address space (CSIOPORT). The page register is connected to the D3–D0 lines.
The Page Register address is CSIOPORT + 18H. The page register outputs are P3–P0,
which are fed into the PAD. This enables the host microcontroller to enlarge its address
space by a factor of 16 (there can be a maximum of 16 pages). See Figure 9.
A16–A19
Inputs
If one or more of the pins PC0, PC1 PC2 and CSI/A19 are configured as inputs, the
configuration bits CADDHLT and CATD define their functionality inside the part. CADDHLT
determines if these inputs are to be latched by the trailing edge of the ALE or AS signal
(CADDHLT = 1), or enabled into the ZPSD3XX at all times (CADDHLT = 0, transparent
mode). CATD determines whether these lines are high-order address lines, that take part in
the derivation of EPROM select signals inside the chip (CATD = 1), or logic input lines that
have no impact on memory or I/O selections (CATD = 0). Logic input lines typically
participate in the Boolean expressions implemented in the PAD B. Unused input pins
should be tied to V
CC
or GND.
EPROM
Size
EPROM
Architecture
EPROM Bank
Architecture
(8 ea)
Device
x8
x16
x8
x16
ZPSD301
256Kb
32K x 8
16K x 16
4K x 8
2K x 16
ZPSD311
ZPSD302
ZPSD312
ZPSD303
ZPSD313
ZPSD304R
ZPSD314R
256Kb
512Kb
512Kb
1Mb
1Mb
2Mb
2Mb
32K x 8
64K x 8
64K x 8
128K x 8
128K x 8
256K x 8
256K x 8
–
4K x 8
8K x 8
8K x 8
16K x 8
16K x 8
32K x 8
32K x 8
–
32K x 16
–
64K x 16
–
128K x 16
–
4K x 16
–
8K x 16
–
16K x 16
–
相關(guān)PDF資料
PDF描述
ZPSD303 Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
ZPSD313 Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
ZPSD301V Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，16K位SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入)
ZPSD304R Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，無SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
ZPSD304RV Field Programmable Microcontroller Peripherals(可編程邏輯,零功耗，無SRAM,19個(gè)可編程I/O,通用PLD有16個(gè)輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ZPSD312-15LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD312-15LM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD312-15U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD312-15UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
ZPSD312-70J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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