參數(shù)資料
型號: ZL50118GAG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Connector assemblies, Network cables;
中文描述: SPECIALTY TELECOM CIRCUIT, PBGA324
封裝: 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034, BGA-324
文件頁數(shù): 70/95頁
文件大?。?/td> 1157K
代理商: ZL50118GAG
ZL50115/16/17/18/19/20
Data Sheet
70
Zarlink Semiconductor Inc.
12.1.2 ST-BUS Master Clock Mode
Figure 27 - TDM Bus Master Mode Timing at 8.192 Mbps
Data Format
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
ST-BUS
8.192 Mbps
mode
TDM_CLKo Period
t
C16OP
t
C16OH
t
C16OL
t
C4OP
t
C4OH
t
C4OL
t
FOD
54.0
61.0
68.0
ns
TDM_CLKo High
23.0
-
37.0
ns
TDM_CLKo Low
23.0
-
37.0
ns
ST-BUS
2.048 Mbps
mode
TDM_CLKo Period
237.0
244.1
251.0
ns
TDM_CLKo High
115.0
-
129.0
ns
TDM_CLKo Low
115.0
-
129.0
ns
All Modes
TDM_F0o Delay
-
-
25
ns
With respect to
TDM_CLKo
falling edge
TDM_STo Delay
Active-Active
t
STOD
-
-
5
ns
With respect to
TDM_CLKo
falling edge
TDM_STo Delay
Active to HiZ and
HiZ to Active
t
DZ
, t
ZD
-
-
33
ns
With respect to
TDM_CLKo
falling edge
TDM_STi Setup Time
t
STIS
5
-
-
ns
With respect to
TDM_CLKo
TDM_STi Hold Time
t
STIH
5
-
-
ns
With respect to
TDM_CLKo
Table 25 - TDM ST-BUS Master Timing Specification
Channel 127 Bit 0
Channel 0 Bit 7
Channel 0 Bit 6
B0
B7
B6
Ch 127 Bit 0
Ch 0 Bit 7
Ch 0 Bit 6
t
STOD
t
STOD
t
FOD
t
FOD
t
STIH
t
STIS
t
STIH
t
STIS
t
C16OP
TDM_CLKO
TDM_F0o
TDM_STi
TDM_STo
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